Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"LFSR"”.
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On the Computation of LFSR Characteristic Polynomials for One-Dimensional and Two-Dimensional Test Pattern Generation
… a predetermined linear feedback shift register (LFSR) in order to generate or decompress deterministic test patterns. As a direct consequence, the test pattern computation and the fault coverage are constrained to the preselected architecture. Work has been done to determine desirable …
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Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
… first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the …
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Efficient Architecture and Implementation for NTRU Based Systems
… are proposed. For NTRUEncrypt system, a new LFSR (linear feedback shift register) based architecture is firstly presented. A novel design of the modular arithmetic unit is proposed to reduce the critical path delay. The FPGA implementation results have shown that the proposed design …
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
… fault coverage achievable with random vectors. LFSR reseeding is used to increase the coverage. However, to achieve satisfactory coverage, one often needs a large number of seeds. Computing a small number of seeds for LBIST reseeding still remains a tremendous challenge, since the vectors needed …
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Cyclic Codes: Low-Weight Codewords and Locators
… often a key ingredient of correlation attacks to LFSR-based stream ciphers. The best general purpose algorithm is based on the generalized birthday problem. In the first part of the thesis I show an alternative approach based on discrete logarithms which has - in some cases relevant for …
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Accelerating Probabilistic Computing with a Stochastic Processing Unit
… simple 19-bit Linear-Feedback Shift Register (LFSR) does not degrade end-point result quality in the tested applications. Therefore, we propose a Stochastic Processing Unit (SPU) with a simple pseudo RNG that achieves equivalent function to RSU-G but maintains the benefit of a CMOS digital …
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Techniques for Enhancing Test and Diagnosis of Digital Circuits
Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an …