Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 35 for “"Instruction-Set-Architecture"”.
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f-DSM: An FPGA-Accelerated Distributed Shared Memory for Heterogeneous Instruction-Set-Architecture Hardware
… architectural trend in this space involves using instruction-set-architecture (ISA) heterogeneity. An exemplar case is emerging I/O devices that include CPU cores with ISAs (e.g., ARM, RISC-V) that differ from that of host CPUs (e.g., x86) and have physically discrete memory. Shared-memory …
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Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
… an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of …
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Accelerating the parsing process with an Application Specific VLSI RISC processor
… the feasibility of designing a specialised instruction set for a RISC like processor able to accelerate the parsing and lexical analysis process, and the physical implementation of a RISC processor in CMOS VLSI technology able to execute the designed instruction set. The feasibility of …
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Machine Code Verification Using The Bogor Framework
… creation of model checking tools specific to the instruction set architecture. The creation of software model checking tools is non-trivial. We present a strategy for using an "off-the-shelf" model checking tool, Bogor, to provide support for multiple instruction set architectures. Our strategy …
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Constructing and evaluating weak memory models
A memory model for an instruction set architecture (ISA) specifies all the legal multithreaded-program behaviors, and consequently constrains processor implementations. Weak memory models are a consequence of the desire of architects to preserve the flexibility of implementing optimizations that …
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Aural imaging from 3D vision
… realtime. Modern processors now contain a SIMD instruction set architecture that can provide substantial improvements in performance when working with specific data types. This program demonstrates a stereo vision algorithm that implements commonly known methods in computer vision and takes …
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Feasibility of Vector Instruction-Set Semantics Using Abstract Monads
Formalizations of instruction-set semantics help establish formal proofs of correctness of both hardware designed to implement these instruction sets and the software implemented against this specification. One such prior work1 formalizes a specification of a subset of the RISC-V instruction-set …
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Flexible MIPS soft processor architecture
The flexible MIPS soft processor architecture borrows selected technologies from high-performance computing to deliver a modular, highly customizable CPU targeted towards FPGA implementations for embedded systems; the objective is to provide a more flexible architectural alternative to …
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Computer-aided design for multilayer microfluidic chips
… control layer. We present a method to define an Instruction Set Architecture as a hierarchical composition of flows. From this specification, we automatically infer and generate the logic and signals to control the chip. To complete the design automation of the control layer, we suggest a routing …
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Eliminating Dynamic Computation Redundancy
… Reuse (CCR) approach integrates compiler and architecture techniques to exploit execution behavior of these regions. In this approach, the Instruction Set Architecture (ISA) provides a simple interface for the compiler to communicate the run-time execution of each region into a hardware …
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Creating a PCI express interconnect in the gem5 simulator
… Interconnect) Express interconnect in the gem5 architecture simulator. The interconnect was designed with the goal of aiding accurate modeling of PCI Express-based devices in gem5 in the future. The PCI Express interconnect that was created consisted of a root complex, PCI Express switch, as …
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Netswap: Network-based Swapping for Server-Embedded Board Clusters
… The project HEXO has explored heterogeneous-Instruction Set Architecture (ISA) server-embedded clusters to minimize the cost. HEXO's key idea is to migrate stateful virtual machines from high-performance x86-based servers to low-power, low-cost ARM-based embedded boards, reducing server's …
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Improving Security of Edge Devices by Offloading Computations to Remote, Trusted Execution Environments
… to push forward the state-of-the-art security on instruction set architecture (ISA) heterogeneous systems by adopting an edge-computing approach. As the embedded devices market grows, such systems remain affected by a wide range of attacks and are particularly vulnerable to techniques that render …
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ZxOS: Zephyr-based Guest Operating System for Heterogeneous ISA Machines
… an array of radically different computing architectures, including multicore and heterogeneous architectures, to continue to accelerate computer performance. An important emerging data point in the heterogeneous architecture design space is heterogeneity in instruction-set architecture …
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A Manufacturing Methodology for Carbon Nanotube-based Digital Systems: from Devices, to Doping, to System Demonstrations
… open-source and commercially available RISC-V instruction set processor, running standard RISC-V 32-bit instructions on 16-bit data and addresses. It integrates >14,000 CMOS CNFETs, and operates as modern microprocessors do today (for example, it can run compiled programs; in addition, we …
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CRIU-RTX: Remote Thread eXecution using Checkpoint/Restore in Userspace
… Prior works have also leveraged heterogeneous instruction set architecture (ISA) systems to improve application performance as well as energy-efficiency, a major cost driver in datacenters, by augmenting high-end servers with power-efficient embedded boards. Existing works, however, suffer from …
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Deep in-memory computing
… the common functional flow across a diverse set of inference algorithms. Based on the analysis, this dissertation presents a multi-functional DIMA to support four algorithms: support vector machine (SVM), template matching (TM), k-nearest neighbor (k-NN), and matched filter. The circuit and …
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A hierarchical approach to the formal verification of embedded systems using MDGs
… microcontroller RT level, the microcontroller Instruction Set Architecture (ISA), the embedded software assembly code level and the embedded software flowchart specification. The correctness of the system hardware platform in implementing its intended architecture is established by formally …
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Leveraging Processor-diversity For Improved Performance In Heterogeneous-ISA Systems
… workloads on multiprocessors with heterogeneous Instruction Set Architecture (ISA) cores. ISA-heterogeneity in processor designs provides a unique dimension for researchers to explore performance benefits through diversity in design choices. Additionally, each application has a natural preference …
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Implementation of Intermittent-robust Computing on RISC-V Architecture
… energy harvesting highlights the need for architectures capable of sustaining correct and reliable execution under frequent and unpredictable power interruptions. This thesis addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level …
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