Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 89 for “"Instruction set"”.
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Instruction set and simulation framework for transactional memory
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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Instruction Set Design for Support of High-Level Languages
Conventional instruction sets or directly interpretable languages (DILs) have not been designed with high-level languages (HLLs) in mind. The resulting semantic gap is known to cause significant inefficiencies in space and time resources in execution. Direct interpretation of HLLs is not the …
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Feasibility of Vector Instruction-Set Semantics Using Abstract Monads
Formalizations of instruction-set semantics help establish formal proofs of correctness of both hardware designed to implement these instruction sets and the software implemented against this specification. One such prior work1 formalizes a specification of a subset of the RISC-V instruction-set …
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Vector Instruction Set Extensions for Efficient and Reliable Computation of Keccak
… as Intel Westmere (and later) and ARMv8 include instruction-level support for the Advanced Encryption Standard (AES), for the Secure Hashing Standard (SHA-1, SHA2) and for carry-less multiplication. These crypto-instructions are optimized for a single algorithm and provide significant performance …
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Strategic adoption of innovation--the case of reduced instruction set computer (RISC) technology
Thesis (Ph. D.)--Massachusetts Institute of Technology, Sloan School of Management, 1994.
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f-DSM: An FPGA-Accelerated Distributed Shared Memory for Heterogeneous Instruction-Set-Architecture Hardware
… architectural trend in this space involves using instruction-set-architecture (ISA) heterogeneity. An exemplar case is emerging I/O devices that include CPU cores with ISAs (e.g., ARM, RISC-V) that differ from that of host CPUs (e.g., x86) and have physically discrete memory. Shared-memory …
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SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors
… architectures of embedded processors: instruction set extensions and multi-core architectures. We show that, with proper processor micro-architecture design and suitable software programming, we are able to deliver SCA-resistant software which performs well in security, performance, and …
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C compiler aided design of application specific instruction set processors using the machine description language LISA
The utilization of application specific instruction-set processors (ASIPs) allows for realizing System-on-Chip (SoC) circuits that are flexible, fast, and energy efficient at the same time. One way to reduce the high ASIP design effort is to create all software tools and hardware models from a …
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Accelerating the parsing process with an Application Specific VLSI RISC processor
… the feasibility of designing a specialised instruction set for a RISC like processor able to accelerate the parsing and lexical analysis process, and the physical implementation of a RISC processor in CMOS VLSI technology able to execute the designed instruction set. The feasibility of …
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Symbolic Execution Over Native X86
… simplify semantics when dealing with a complex instruction set such as the Intel Industry Standard Architecture (ISA) instruction set. However, a question that remains is whether these intermediate languages truly retain semantic fidelity or whether elements of the ISA instruction set get lost …
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Nonvolitional Faking on a Personality Measure: Testing the Influence of Unconscious Processes
… strategies of impression management. A 2 (Instruction Set) x 2 (Personality Feedback) x 2 (Mortality Salience) factorial design addressed social desirability biases in responding to personality measures. There were significant changes in all measures due to volitional (Fake Good) …
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Machine Code Verification Using The Bogor Framework
… creation of model checking tools specific to the instruction set architecture. The creation of software model checking tools is non-trivial. We present a strategy for using an "off-the-shelf" model checking tool, Bogor, to provide support for multiple instruction set architectures. Our strategy …
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Aural imaging from 3D vision
… realtime. Modern processors now contain a SIMD instruction set architecture that can provide substantial improvements in performance when working with specific data types. This program demonstrates a stereo vision algorithm that implements commonly known methods in computer vision and takes …
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Adaptation of a fault–tolerant FPGA–based launch sequencer as a CubeSat payload processor
… is to design and test a fault–tolerant reduced instruction set computer processor running a subset of the multiprocessor without interlocked pipelined stages instruction set. This processor is implemented on a field programmable gate array (FPGA) and will be used as the foundation for a payload …
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Efficient Support for Speculative Tasking
… signatures to software directly through the instruction set. Using SoftBulk, programs can collect information about their own memory access patterns and use that information for a variety of purposes including code optimization and debugging.
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A Manufacturing Methodology for Carbon Nanotube-based Digital Systems: from Devices, to Doping, to System Demonstrations
… open-source and commercially available RISC-V instruction set processor, running standard RISC-V 32-bit instructions on 16-bit data and addresses. It integrates >14,000 CMOS CNFETs, and operates as modern microprocessors do today (for example, it can run compiled programs; in addition, we …
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Instruction Sets for Parallel Random Access Machines
… Random Access Machines (PRAMs) with different instruction sets. A basic PRAM can perform the following operations in unit-time: addition, subtraction, Boolean operations, comparisons, and indirect addressing. Multiple processors may concurrently read and concurrently write a single cell. Let …
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Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
… an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of …
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Run-Time Adaptive Cache Management
… This scheme is fully compatible with existing instruction set architectures. This dissertation also examines the theoretical upper bounds on the cache hit ratio that the proposed techniques can provide, for several integer applications. Then, detailed trace-driven simulations of several integer …
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