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Showing 1 to 8 of 8 for “"IP cores"”.

  1. Enhancing Trust in Reconfigurable Hardware Systems

    … as the typewriter hack involving subversive chips resulting in leakage of keystroke data and hardware backdoors crippling anti-aircraft guns during an attack demonstrate the need to protect all system functions. With more focus on securing a system, trust in untrusted components at the …

    vt Repository record for Enhancing Trust in Reconfigurable Hardware Systems (opens in a new tab)

  2. RHINO software-defined radio processing blocks

    … of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost …

    cape-town Repository record for RHINO software-defined radio processing blocks (opens in a new tab)

  3. Low-Power Reconfigurable Digital Signal Processing

    … on the concept of DAT and intellectual property (IP) core generators. Energy-optimum parameters are obtained via DAT, and are fed into IP core generators, which generate a synthesizable VHDL description of the IP core. The IP cores are synthesized via commercial logic synthesis tools. The proposed …

    uiuc Repository record for Low-Power Reconfigurable Digital Signal Processing (opens in a new tab)

  4. Communication Synthesis for MIMO Decoder Matrices

    … which can hold custom user hardware and IP cores. This framework, which is controlled by a microsequencer, is centered on a matrix-based memory structure comprised of 64 individual dual-ported memory blocks. The microsequencer uses an instruction word that can control every element of the …

    vt Repository record for Communication Synthesis for MIMO Decoder Matrices (opens in a new tab)

  5. Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation

    Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First, offshore chip manufacturing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the …

    vt Repository record for Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation (opens in a new tab)

  6. Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware

    … hardware Trojan threats in third-party IP cores, and preserving stability in process control systems. High-level architectures demonstrated with prototypes are presented for the selected applications. Implementation results illustrate the RETC efficiency in terms of the performance and …

    vt Repository record for Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware (opens in a new tab)

  7. Translation of Heterogeneous High-level Models to Lower Level Design Languages

    … to build complex systems. Historically, chip design companies have always reused designs in going from one product generation to another, but the efficiency of bottom-up design is enhanced by the use of IP (Intellectual Property) cores that a company can buy from an outside source. Design …

    vt Repository record for Translation of Heterogeneous High-level Models to Lower Level Design Languages (opens in a new tab)

  8. Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems

    … procedures, as the reusability of the on-chip decoder for the testing of multiple cores, the reusability of the tester vector memory (local memory of the test head), the on-chip implementation cost of the decoder and the test power consumption. Moreover, we improve each of the aforementioned …

    patras-thes Repository record for Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems (opens in a new tab)