Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"IP core"”.
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Low-Power Reconfigurable Digital Signal Processing
… on the concept of DAT and intellectual property (IP) core generators. Energy-optimum parameters are obtained via DAT, and are fed into IP core generators, which generate a synthesizable VHDL description of the IP core. The IP cores are synthesized via commercial logic synthesis tools. The proposed …
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Ein Ansatz für die Nutzung teildefekter Field Programmable Gate Arrays (FPGAs) in der Serienproduktion
… verteilt: 1. Bereitstellung von defekttoleranten IP-Core-Versionen / 2. Erstellung einer defekttoleranten FPGA-Konfiguration bei Einhaltung von zeitlichen Anforderungen an das Design / 3. Anpassung dieser Konfiguration an jedes defekte FPGA innerhalb der Serienproduktion.
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Multimedia session continuity in the IP multimedia subsystem : investigation and testbed implementation
The advent of Internet Protocol (IP) based rich multimedia services and applications has seen rapid growth and adoption in recent years, with an equally increasing user base. Voice over IP (VoIP) and IP Television (IPTV) are key examples of services that are blurring the lines between traditional …
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Applying Universal Verification Methodology on a Universal Asynchronous Receiver/ Transmitter design
… for serial communication over a computer or a peripheral device. The UART protocol accepts the input data as bytes and transmits the single bits in a sequential way. Usually, there will one or more UART peripherals which are integrated in microcontrollers and related devices which can support …
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Implementation and Performance Evaluation of an NGN prototype using WiMax as an Access Technology
Telecommunications networks have evolved to IP-based networks, commonly known as Next Generation Networks (NGN). The biggest challenge in providing high quality realtime multimedia applications is achieving a Quality of Service (QoS) consistent with user expectations. One of the key additional …
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Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation
Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First, offshore chip manufacturing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the …
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Output space compaction for testing and concurrent checking
In der Dissertation werden neue Entwurfsmethoden für Kompaktoren für die Ausgänge von digitalen Schaltungen beschrieben, die die Anzahl der zu testenden Ausgänge drastisch verkleinern und dabei die Testbarkeit der Schaltungen nur wenig oder gar nicht verschlechtern. Der erste Teil der Arbeit …
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios
… interfacing to Gigabit Ethernet (GbE) and Peripheral Component Interconnect Express (PCIe) bus. Gateware for programming FPGAs is described at a lowlevel of design abstraction using Register Transfer Language (RTL), typically using either VHSIC-HDL (VHDL) or Verilog code. In practice, the …
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Study of Radiation Effects on FPGA and GPU based Neural Networks Accelerator Designs
… proposed in this area of research, such as triple modular redundancy (TMR) , error-correcting codes (ECCs), etc., but the effectiveness of these designs gradually decreases as the technology node continues to shrink. Therefore, as IC technology continues to evolve, improving its radiation …