Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 47 for “"IC Design"”.
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A cost quality model for CMOS IC design
… integration (VLSI) complementary metal oxide semiconductor (CMOS) technology, the number of transistors that can be integrated on a single chip is increasing rapidly. Ensuring that these extremely dense chips are almost free of defects, and at the same time, cost-effective requires planning from …
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Digitally-Assisted RF IC Design Techniques for Reliable Performance
<p>Semiconductor industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage …
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Mixed-Signal IC design for Heterogeneously Integrated Multi-Analyte Chemical Sensor Arrays
… sensor nodes are emerging in a wide range of critical applications such as environmental monitoring, health applications, home automation and military surveillance and reconnaissance. The addition of low power wireless capability to such sensor nodes allows communication between a node and a base …
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Machine learning for analog/mixed-signal IC design : scaling from circuits to systems
… circuits are widely used in many emerging applications, and the increasing demand calls for a shorter design cycle and time-to-market. Traditionally the design process is dominated by manual efforts and is very time-consuming, which involves design experts iterating between the circuit sizing …
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Fully Distributed Control and Its Analog IC Design For Scalable Multiphase Voltage Regulators
Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power …
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Energy Harvesting IC Design for an Electromagnetic Generator Based on the Split Capacitor Approach
… harvest vibrational energy via an electromagnetic generator (EMG). The proposed circuit intends to extract maximum power from the EMG by utilizing the maximum power transfer theorem which states that maximum power is transferred to the load when the source resistance equals the load resistance. …
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Vibration Energy Harvesting IC Design with Incorporation of Two Maximum Power Point Tracking Methods
The proposed vibration energy harvesting IC harvests energy from a piezoelectric transducer (PZT) to provide power for a wireless sensor node (WSN). With a traditional rectification stage, a two-path three-switch dual-input dual-output architecture is adopted to extract power and regulate the …
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Low Power IC Design with Regulated Output Voltage and Maximum Power Point Tracking for Body Heat Energy Harvesting
… be harvested from body heat using thermoelectric generators, or TEGs. TEGs provide a continuous, scalable, solid-state energy source ideal for wearable and wireless electronics and sensors. Unfortunately, current TEG technology produces low power (< 1 mW) at a very low voltage (20-90 mV) and …
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Integrated circuit control of resonant and hard switched dc/dc converters for industrial and educational applications
… an integrated secondary side synchronous rectification controller, designed on a modern industrial silicon IC process, for use in the LLC resonant converter topology. The controller is intended to function in systems with output power levels up to 500 W and switching frequencies up to 1 MHz. …
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VC's decision factor in semiconductor investment
… thesis examines the relationship between the semiconductor industry and venture capital ("VC") industry in China and Taiwan. Taiwan has established an impressive semiconductor industry by encouraging high technology investment for the past two decades; on the other hand, Mainland China is …
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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. …
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Analysis of MOS Current Mode Logic (MCML) and Implementation of MCML Standard Cell Library for Low-Noise Digital Circuit Design
<p>MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design …
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Dynamic scan chains : a novel architecture to lower the cost of VLSI test
Fast developments in semiconductor industry have led to smaller and cheaper integrated circuit (IC) components. As the designs become larger and more complex, larger amount of test data is required to test them. This results in longer test application times, therefore, increasing cost of testing …
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A low-noise bandgap voltage reference employing dynamic element matching
Bandgap voltages references are widely used in IC design, but are sensitive to low-frequency noise and component mismatch. This thesis describes the design and testing of a new IC voltage reference that targets these issues through three dynamic element matching (DEM) subsystems. The first is a …
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ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS
Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring …
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Transistor-Level Programmable Fabric
We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. This TRAnsistor-level Programmable (TRAP) fabric allows …
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Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing
… is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of …
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SSTA design methodology for low voltage operation
Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor parameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new …
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Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration
Design of modern mixed signal integrated circuits is becoming increasingly difficult. Continued MOSFET scaling is approaching the global power dissipation limits while increasing transistor variability, thus requiring careful allocation of power and area resources to achieve increasingly more …
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