Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 17 of 17 for “"High-speed Links"”.
-
Channel coding for high speed links
… explores the benefit of channel coding for high-speed backplane or chip-to-chip interconnects, referred to as the high-speed links. Although both power-constrained and bandwidth-limited, the high-speed links need to support data rates in the Gbps range at low error probabilities. Modeling …
-
Fractionally spaced equalization for high-speed links
As high-speed links enter the multi-Gb/s era, equalization and clock recovery designs become much more challenging. For conventional links, these two loops are separate with different performance metrics, resulting in sub-optimal performance. Fractionally spaced equalization (FSE) inherently …
-
Channel-and-circuits aware, energy-efficient coding for high speed links
Throughput and energy-efficiency of high-speed chip-to-chip interconnects present critical bottlenecks in a whole range of important applications, from processor-memory interfaces, to network routers. These links currently rely solely on complex equalization techniques to maintain the bit error …
-
A low cost asynchronous eye diagram reconstruction system for high speed links
As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low …
-
Equalization in continuous and discrete time for high speed links using 65 nm technology
"With the rapid growth of technology in areas such as the internet-of-things (IOT), network infrastructure, big data, etc., there has grown a need for low power and low cost integrated solutions in order to meet the specifications of these larger scale systems. Currently, many semiconductor …
-
Design of a phase locked loop based clocking circuit for high speed serial link applications
… the driving forces leading the innovations in high-speed interfaces. With the rise of heavy duty data centers to handheld mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high and has led the roadmap of the semiconductor industry, …
-
Transistor level X-parameter simulations of equalization circuits
… circuit designers must deal with. Specifically, high-speed links have been the focus of much of the research into mitigating signal integrity issues. To combat the effects of jitter and other signal integrity problems, circuit designers have begun using increasingly more complex circuitry …
-
Package and PCB solutions for high-speed data link applications
Continual increase in high-speed transfer rates is essential in today's world in order to keep up with Moor's law scaling and to meet application demands. This increase in information transfer rates is essentially limited by the bandwidth of the communication channel. Channel loss, signal …
-
Prioritization, security and relay selection in network coded multiple access relay networks
… With ever growing need for reliable high speed links, Cooperative communication and Network coding have emerged as viable technologies to bridge the gap.</p> <p>In today's wireless network, different users have different demands for reliability based on their respective application. …
-
Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration
… process. The situation is particularly acute in high-speed links. As an important building block of many systems (high speed I/O, on-chip communication, ...) power efficiency and area footprint are of utmost importance. Design of these systems is challenging in both system and circuit domain. On …
-
An Experimental Investigation of TCP Performance in High Bandwidth-Delay Product Paths.
… providing a reliable transport service to higher layer applications. Second, it enforces congestion control. That is, it seeks to match the rate at which packets are injected into the network to the available network capacity. A particular aim here is to avoid so-called congestion collapse, …
-
Design of all digital phase-locked loop in serial link communication
The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In particular, wireline inter-IC communications systems such as broadband Internet, multi-core CPU and system-on-chip have fueled the …
-
Clock synthesizer design with analog and digital phase locked loop
… communication protocols is at an all-time high. This trend, together with the widespread presence of broadband Internet, multi-core CPU and system-on-chip designs have pushed the demand for data rate in wireless and wireline links into multi-Gbps ranges. In order to fulfill the increasing …
-
Using x-parameters for signal integrity applications
… buffers are the nonlinear terminations of the high-speed links that the signal integrity engineer is tasked with designing and optimizing. Brief treatments of the X-parameter formalism, the harmonic balance simulation method, the latency insertion method, and the Input/Output Buffer Information …
-
The significance of transients following failures and repairs in packet-switched networks
… communication networks, which consist of highly reliable high-speed links and switching nodes, it is argued that the steady-state assumption is justified on the basis of the large difference in rates of traffic-related events, such as call completions and packet transmissions, compared to …
-
Dynamic power management for computing and communication
… for short-reach on-board chip to chip links. In this thesis, we explore power scaling techniques for on-chip high-speed links. To this end, A 10Gb/s rapid-on/off on-chip link transceiver is presented to demonstrate the architecture and circuit techniques to improve energy efficiency …
-
Eye diagram modeling and statistical simulation in nonlinear high-speed link systems
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-09-16 without embargo terms