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Showing 1 to 12 of 12 for “"High-speed I/O"”.
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.
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System-Aware Design of Energy-Efficient High-Speed I/O Links
Today's high-speed I/O links operate under stringent specifications: few tens of Gb/s data rates over 20 inches of copper trace, power efficiencies of the order of 10-to-30 mW/Gb/s and a bit error-rate (BER) target of 10^(-12) or lower. State-of-the-art I/O links consist of a transmit driver, PLL, …
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Analog and mixed-signal circuitry for system-assisted high-speed I/O links
The state-of-the-art design methodology for high-speed I/O links is to specify component-level design requirements to achieve high-fidelity component-level performance. While designing each component in the link with high fidelity guarantees a reliable link, it does not inherently optimize the link …
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The effect of on-chip ESD protection on reliable high-speed I/O link equalization power consumption
… designer. In this work, the ESD protection on high-speed serial I/O link performance is investigated. Simulations are used to determine the effect of the parasitic ESD capacitance on the equalization required to maintain a specific bit error rate (BER). Then, the simulation results are …
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Noise -Tolerant Digital System Design
… to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling …
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Bridging the gap : an optimization-based framework for fast, simultaneous circuit & system design space exploration
… process. The situation is particularly acute in high-speed links. As an important building block of many systems (high speed I/O, on-chip communication, ...) power efficiency and area footprint are of utmost importance. Design of these systems is challenging in both system and circuit domain. On …
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Charged device model electrostatic discharge protection and test methods for integrated circuits
… useful because they do not add capacitance to high-speed nodes. The effectiveness of diode vs. diode-triggered silicon controlled rectifier (DTSCR) protection in high-speed I/O cells is examined. The industry standard for CDM characterization of a product is field-induced CDM (FICDM) testing of …
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Clock synthesizer design with analog and digital phase locked loop
… communication protocols is at an all-time high. This trend, together with the widespread presence of broadband Internet, multi-core CPU and system-on-chip designs have pushed the demand for data rate in wireless and wireline links into multi-Gbps ranges. In order to fulfill the increasing …
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… the driving forces leading the innovations in high-speed interfaces. With the rise of heavy duty data centers to handheld mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high and has led the roadmap of the semiconductor industry, …
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Crosstalk mitigation of high-speed interconnects using modal signaling
Today's high-speed I/O signaling links are faced with difficult challenges: due to manufacturing and technology limitations, the resources (pins and interconnects) available for off-chip signaling remain almost constant, while the throughput needed is increasing and the required aggregate …
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Design of energy-efficient high-speed wireline transceiver
… many applications ranging from mobile devices to high-performance processors. The power problem permeates both computing and communication systems alike. Especially in the era of Big Data, continuously growing demand for higher communication bandwidth is driving the need for energy-efficient …
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Design of reliable and energy-efficient high-speed interface circuits
DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44