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Showing 1 to 2 of 2 for “"High-k gate stack"”.
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Addressing performance bottlenecks for top-down engineered nanowire transistors
… allowed CMOS technology to meet the demands of higher device density, faster clock rate and lower power consumption. However, as the scaling dimensions shrink down to the sub-100 nm regime, immense physical challenges make the use of conventional scaling techniques alone insufficient. Novel …
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TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer
Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO_2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been …