Global ETD Search
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Showing 1 to 5 of 5 for “"High speed serial link"”.
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… the driving forces leading the innovations in high-speed interfaces. With the rise of heavy duty data centers to handheld mobile devices, the desire for faster, low-power integrated inter-IC communication protocols is at an all-time high and has led the roadmap of the semiconductor industry, …
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Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
… equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock …
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Design of a clock and data recovery circuit in 65 nm technology
… fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive for more …
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Transparent Asynchronous Transmitter Receiver Interface (TAXI) communications for fiber optic data links
Serial or parallel data links have been the primary tools of data transfer across physical layer boundaries for point-to-point communication systems. However there exists a tradeoff between these two kinds of data transfer mechanisms based on their cost-effectiveness and complexity. A recent …
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Energy-efficient wireline transceivers
Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are …