Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Hardware Reliability"”.
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Design and implementation of a hardware reliability simulator for multiple component systems.
Reliability is a critical feature in systems which perform a critical safety or economic role as failure can result in catastrophic loss. There is a need to demonstrate that such systems will perform as required but the ability to do this is restricted by the available techniques. Conventional …
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SWAT: Designing Resilient Hardware by Treating Software Anomalies
… shows, for the first time, that a comprehensive hardware reliability solution can be realized by treating the software-level symptoms caused by both permanent and transient hardware faults. The presented work lays the foundation for the SWAT approach and paves the way for future work on low-cost …
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Mobile RFID system for inventory automation
… an RFID reader is also implemented to test hardware reliability and the feasibility of a grounded robot to perform inventory in a three dimensional space.
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Algorithmic approaches to enhancing and exploiting application-level error tolerance
… to have largely stochastic characteristics, hardware reliability has become a first-order design concern. To make matters worse, emerging computing systems are becoming increasingly power constrained. Traditional hardware/software approaches are likely to be impractical for these power …
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Preserving application reliability on unreliable hardware
… becoming increasingly susceptible to in-field hardware failures from sources such as high-energy particle strikes (or soft-errors). This reliability threat is expected to affect a broad computing market motivating the need for very low cost resiliency solutions. Software anomaly based hardware …
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Dafny-HLS: verified and optimized high-level synthesis via MLIR with LLM-assisted bug repair
High-Level Synthesis (HLS) improves hardware design productivity by generating Register-Transfer Level (RTL) from high-level language descriptions (e.g., C/C++). While recent MLIR-based HLS frameworks enable multi-level optimization and automated design space exploration, they are based on the …
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Optimizing performance under thermal and power constraints for HPC data centers
… Recent reports have expressed concern that reliability at the exascale level could degrade to the point where failures become a norm rather than an exception. HPC researchers are focusing on improving existing fault tolerance protocols to address these concerns. Research on improving …