Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 77 for “"Hardware Architecture"”.
-
A circuit based Evolvable Hardware Architecture
This thesis presents an Evolvable Hardware Architecture that was developed in the Quantum Nanostructures and Nanofabrication Laboratory. We believe intrinsic evolution is a promising tool that can be used to exploit the physics of complex systems. I present a reconfigurable analog circuit platform …
-
Puppetmaster: a certified hardware architecture for task parallelism
This thesis presents Puppetmaster, a hardware accelerator for transactional workloads. Existing software and hardware frameworks for transactional memory and online transaction processing are not able to scale to hundreds or thousands of cores unless the rate of conflicts between transactions is …
-
Embedded hardware architecture for multi-parameter physiological signal monitoring
… power, and real-time performance constraints in hardware platforms. This thesis focuses on achieving balanced and efficient hardware-based solutions for health monitoring techniques that provide reasonably accurate abnormal event detection results but at the same time are cost-effective from the …
-
Mixed-precision NN accelerator with neural-hardware architecture search
Neural architecture and hardware architecture co-design is an effective way to enable specialization and acceleration for deep neural networks (DNNs). The design space and its exploration methodology impact efficiency and productivity. However, both architecture designs are challenging. We first …
-
A Hardware Architecture for GPS/INS-Enabled Wireless Sensor Networks
… with GPS receivers. This research proposes a hardware architecture for location-based wireless sensor networks. In this architecture, each sensor node consists of a GPS receiver, a reduced set of low cost micro-electro-mechanical-system-based INS and a wireless transceiver. Sensor nodes in WSN …
-
An optimized hardware architecture and communication protocol for scheduled communication
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
-
A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware
A new design methodology that produces hardware solutions for performing real-time image processing is presented here. This design methodology provides significant advantages over traditional hardware design approaches by translating real-time image processing tasks into the gate-level resources of …
-
A MIPS datapath simulator for enhancing visual learning of computer architecture
… tool for visually teaching the fundamentals of hardware architecture. Built over the 2019-2020 academic year, the Simulator allows course staff and students to virtually build and explore hardware architecture circuits. The Datapath Simulator is built around the MIPS architecture and supports …
-
Acceleration of asymptotic computational electromagnetics physical optics — shooting and bouncing ray (PO-SBR) method using CUDA
… parallel nature of the method. NVIDIA GPU’s hardware architecture is then described to show the portability of the method onto GPU devices. Then, NVIDIA’s GPU pro-gramming environment, CUDA, is introduced for the implementation of the part of the method to be parallelized. Finally, this …
-
Hardware and software architecture for non-contact, non-intrusive load monitoring
… This thesis presents three new developments: a hardware architecture that measures the electromagnetic fields surrounding a multi-conductor cable, calibration methods to noninvasively determine a mapping from the sensed fields to power transmission, and a software framework that enables …
-
The Effectiveness Of Data Codes And Hardware Selection To Mitigate Scintillation Effects On Free Space Optical Data Transmission
… for error correction, amplitude modulation and hardware architecture schemes. This study simulated the use of arrays and large apertures for the receiving devices, and compared the resultant scintillation index with the theoretical calculations.
-
A hardware acceleration technique for gradient descent and conjugate gradient
… we target. In this thesis we present a novel hardware architecture for accelerating gradient descent and other similar algorithms. To support this architecture, we also present a sparse matrix-vector storage format, and software support for utilizing the format, so that it can be e ciently …
-
Power And Hotspot Modeling For Modern GPUs
… of them estimate power at a higher level than architecture, which are therefore missing hardware reconfigurability. In this thesis, we propose a framework that models power and heat dissipation at the hardware architecture level, which allows for configuring and investigating individual …
-
Parallelizing the GSM speech compression algorithm on Raw
… was parallelized on Raw, a highly distributed hardware architecture with low latency communication. Parallelization architectures designed included a 2-stage pipeline and a 5-node satellite-hub model for distributing the time-intensive correlation calculations. Two additional architectures …
-
Simulation and Design of Quantum Processors for Low‑Overhead Quantum Error Correction
… investigates the simulation and design of the hardware architecture required for large‑scale quantum error correction (QEC). Specifically, we design microwave circuits for fast and high‑fidelity readout and devise a long‑range coupler (LRC) that spans five qubit lattice sites, suitable for …
-
Architectures for e-Textiles
… a simulation environment creates a new software/hardware architecture with widely useful implementations in wearable and large-area computational systems. The software environment acts as a functional modeling and testing platform, providing estimates of design metrics such as power consumption. …
-
Algorithms, architectures and circuits for low power HEVC codecs
… this complexity in the context of real-time hardware video codecs. Our work focused on two specific areas: Motion Compensation Bandwidth and Intra Estimation. HEVC uses larger filters for motion compensation leading to a significant increase in decoder bandwidth. We present a novel motion …
-
Real-Time Computational Scheduling with Path Planning for Autonomous Mobile Robots
… data collection in the real-world with all hardware and software combined. This thesis focuses on the implementation of various computational loads (i.e. scheduler, path planner, RGB-D camera, object detection, depth estimation, etc.) on the NVIDIA Jetson AGX Xavier and real-world …
-
Dataset for Machine Learning Based Cache Timing Attacks and Mitigation
… partitioning, OS kernel isolation, and various hardware/operating system enhancements, have similarly progressed. Nonetheless, side-channel attacks necessitate effective and efficient prevention mechanisms or alterations to hardware architecture. Recently, machine learning (ML) is an emerging …
-
A Solar-Powered and Multi-Tiered Mesh Node for a Portable In Situ Emergency Response System
… design of the PERPETUU node is a multi-tiered hardware architecture-the system combines a low-power micro-controller, a medium-power Wifi module, and a high-power micro-processor to provide large spectrum of power states. In addition to being able to detect survivors using a low-power Wi-Fi …
Page 1 of 4