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Showing 1 to 1 of 1 for “"Half adder"”.
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Robust and reliable hardware accelerator design through high-level synthesis
… architectures consisting entirely of full-adder standard cells; (2) minimum-area modulo adder and subtractor architectures; (3) an array-based modulo multiplier design; and (4) a modulo equality comparator that handles the residue encoding produced by the above. We compare our new …