Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 23 for “"HSPICE"”.
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Simulation of IBIS models using HSpice and ADS
… circuit simulators: specifically Synopsys HSpice and Agilent Advanced De- sign System (ADS). IBIS has become widely accepted in industry due to the fact that it protects the intellectual property of vendors and because of its standardized format which allows it to be integrated with many …
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Study of design tradeoffs of DRAM and SRAM memories, using HSPICE computer simulation
… was optimized using circuit simulation software, HSPICE, to observe DRAM and SRAM waveforms. With TSMC 0.18 micron technology, minimum cycle times of 2.1 ins (DRAM) and 1.1 8ns (SRAM) were achieved (Cbl = 100FF), by optimizing the kr values of the SA transistors, for a fixed SA area of 1 …
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Cell-based array for deep sub-micron technologies
… involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital …
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Circuit level delay and power analysis of graphene nano-ribbon field-effect transistors using monte carlo simulations and standard cell library characterization
… gate- level impact of the different technology. HSPICE based simulations are per- formed to study smaller circuits and the pros and cons of using GNR transistors. Monte Carlo simulations are performed to analyse the sensitivity of delay and power to the change in transistor parameters and also to …
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Numerical Modeling of Multi-Conductor Interconnects for High Speed Integrated Circuits
… using a commercial circuit simulator like HSPICE. The methodology has been numerically verified and implemented in the form of some select interconnecting scenarios for typical on-chip applications. The new methodology has also been compared with the previous methodology for robustness, …
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Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool
… and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with …
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Circuit-Level Modeling and Simulation of Semiconductor Lasers
… The first approach, implemented in both HSPICE and SABER, is a simple thermal model which incorporates a temperature-dependent offset current into the standard laser rate equations in order to describe thermally dependent threshold current and output-power rollover in the LI …
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Design and simulation of a PCI Express Gen 3.0 communication channel
… 3.0 speeds. Simulation software tools such as HSPICE, Ansoft HFSS, Ansoft Via Wizard 3.0 and MATLAB were utilized. A simulation model of the system functioning under PCIe Gen 3.0 specifications was successfully developed by using CTLE equalization technique.
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Integrated Sensing and Computing Architectures Enabling Smart Vision Sensors
… simulation speedups of over 25,000x compared to HSPICE. Collectively, these contributions provide a cohesive blueprint for the next generation of intelligent, efficient, and secure edge vision systems.
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Multivariable analysis of spectral measurements for the characterization of semiconductor processes
… for CMP, simulating the thermal behavior using Hspice circuit simulation software, and verifying this model against experimentally measured thermal behavior in CMP.
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Vibration-to-electric energy conversion using a mechanically-varied capacitor
… the experimental charge pump near 1.56 kHz. HSPICE simulation confirms that given a maximum to minimum capacitance ratio larger than 1.65 and realistic models for the transistor and diodes, the circuit can harvest approximately 1 lW of power. This power level is achieved after optimizing the …
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Digital to Analog Converter Design using Single Electron Transistors
… SET DAC designs and characterize them with an HSPICE SET simulation model. The first design is a charge scaling architecture similar to what is frequently used in CMOS. The second two designs are based on a current steering architecture, but are unique in their implementation with SETs.
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A micromachined silicon vibrating-beam angular rate sensor : a design and implementation study
… electrical components of the sensor is built in HSPICE and used to simulate the basic operation of the sensor. To improve the mismatch between beam resonant frequencies, a scheme of novel Concave Corner Compensation Patterns is devised to substantially reduce the size of the residual 111 flanges …
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A systematic methodology to improve CMOS transductors for low power and wideband operation
… derivations, numerical calculations as well as HSPICE simulations on various transconductor structures are conducted to prove the effectiveness of the proposed optimization methodology. Two test chips are also fabricated and measured to verify the analyses. A few transconductor-based analog …
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VALIDATION OF CIRCUIT TIMING BEHAVIOR IN THE PRESENCE OF DELAY DEFECTS AND NBTI AGING
… The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.
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Analysis and Mitigation of Multiple Radiation Induced Errors in Modern Circuits
… the proposed methodology matches closely with HSPICE while providing a speedup of 15X. The analysis of the soft error rate of a circuit has continued to be a difficult problem due to the calculation of the logical effect on a pulse generated by a radiation particle. Common existing methods to …
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Novel RTD-Based Threshold Logic Design and Verification
… based on Shannon Expansion, as well as the HSPICE simulation results of the programmable and primitive RTD/HFET gates that we have designed. An efficient control bit generating algorithm is developed by using a special encoding scheme to implement any given logic function. In addition, we …
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A novel approach to embedding memory with crosstalk logic circuits for high performance applications
… circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed with the equivalent static CMOS circuits to compare the number of transistors, performance, and power. It is observed that the number of transistors consumed by the CBML logic circuits like 3-input AND, OR, is 40% …
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Design and Analysis of Defect- and Fault-tolerant Nano-Computing Systems
… redundancy-delay trade-off analysis using HSPICE. SETRA (Scalable, Extensible Tool for Reliability Analysis) has been specifically designed for analyzing nanoscale CMOS logic architectures with DTMCs. SETRA also integrates well with current industry-standard CAD tools. It has been shown …
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Static random-access memory designs based on different FinFET at lower technology node (7nm)
… process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] – [4]. Scaling of technology have degraded the performance of CMOS designs …
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