Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"Fully-depleted"”.
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Optimal design of channel doping for fully depleted SOI MOSFETs
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
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A high-speed, low-power analog-to-digital converter in fully depleted silicon-on-insulator technology
… analog-to-digital converter fabricated in a fully depleted silicon-on-insulator CMOS technology. Silicon-on-insulator CMOS technology provides a number of benefits for low-power low-voltage analog design. The full dielectric isolation of the silicon island, where the transistors are …
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Electron transport in ultrathin-body fully depleted n-MOSFETS fabricated on strained silicon directly on insulator with body thickness ranging from 22nm to 25 nm
The electron effective mobility in ultrathin-body (UTB) n-MOSFETs fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage …
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Device design and process technology for sub-100 nm SOI MOSFET's
… so that the channel is either partially- or fully-depleted-of majority carriers. Partially-depleted (PD) SOI MOSFET's are easier to manufacture than fully-depleted (FD) SOI MOSFET's because a thicker SOI film can be used. However, PDSOI MOSFET's are difficult to design due to floating-body …
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The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs
Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control …
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Pipelined oversampling analog-to-digital converters
… with hundreds of stages feasible by providing fully-depleted operations which are highly accurate, low power, simple, and compact. Other operations are performed using nondepleted circuits.
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Active pixel sensors for X-ray astronomy
… Technology Group. APS-1 is fabricated in a fully depleted silicon-on-insulator (FDSOI) technology. FDSOI is especially well-suited to produce a scientific x-ray imager. The device includes sixteen different pixel variations to determine the processing parameters that can produce the best …
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Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process
… are being developed as successors, such as fully depleted silicon-oninsulator (FD-SOI), Multigate MOSFET, FinFETs, among others, and new design techniques emerge by taking advantage of the improved features of these devices. This thesis focused on the development of analytical expressions …
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Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures
… Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to …
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A high speed serializer/deserializer design
… of the PLL clock using a three dimensional fully depleted silicon on insulator (3D FDSOI) CMOS process. The 3D process separated the analog PLL portion from the digital calibration portion into different tiers. This eliminated the noise coupling through the common substrate in the 2D …
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Projection of TaSiOx/In0.53Ga0.47As Tri-gate transistor performance for future Low-Power Electronic Applications
… to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering …
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SiGe-on-insulator and strained-Si-on-insulator for strained-Si CMOS and nanocrystalline-Ge waveguides
… Such ultra-thin SSOI substrates are ideal for fully-depleted CMOS, in comparison to some thicker SGOI substrates that were fabricated, which are required for partially-depleted CMOS. SGOI substrates can also be used as a platform for novel photonic devices. In this work, one such example is …
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Technologies for Scaling Silicon-MOS Quantum Processors
… noise. Secondly, we investigate devices based on Fully-Depleted Silicon-On-Insulator (FDSOI) technology manufactured in a full-scale 300mm wafer process as a platform for quantum dot based quantum processors. A double-nanowire device is configured such that a 2x2 array of quantum dots is formed in …
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Electron-reflector strategy for CdTe thin-film solar cells
… thin (less than 2 μm) CdTe cells which have a fully-depleted CdTe absorber layer. Thin CdTe cells can also benefit from the optical reflection at the back surface. To investigate the possibility of still higher efficiency, both electron and optical reflection were numerically applied to the …
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Toward the end of the MOSFET roadmap : investigating fundamental transport limits and device architecture alternatives
… for bulk silicon NMOSFETs and FDSOI (Fully-Depleted Silicon-On-Insulator) alternatives, focusing on the 50 and 25 nm Leff generations. Scaling of bulk MOSFETs well below 100 nm Leff requires heavy channel doping, leading to degraded low-field mobility. Provided that the gate …
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Modeling and simulation of nano-scale transistor
… improved compared with the previous source fully depleted approximation. ☐ Based on the above electric potential model, the Kane’s tunneling formula is utilized for the calculation of band-to-band tunneling current. The model is proven to be accurate in all operating regions. Unlike the 1-D …