Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 10 of 10 for “"Full adder"”.
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Design of low power high speed digital vedic multiplier using 13T hybrid full adder
… is omnipresent in most common circuits; and adders act as the main block for the multiplier to operate. Performance of full adder had direct impact in all arithmetic circuits. In this thesis, a 4x4 bit Vedic multiplier has been successfully designed using the combination of Urdhva Triyakbyam …
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Design of a smart power manager for digital communication systems
… power of a NOT gate, a multiplexer circuit, a full adder and a two-bit full adder. The results are compared with OrCAD Cadence simulation for the same circuits. The results show that the new model can simulate the power dissipation accurately under different voltages, frequencies, and different …
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Design of a digital logic trainer
… thesis, particularly in the development of the Full Adder, would allow for the design of any moderately complex digital system.
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A novel approach to embedding memory with crosstalk logic circuits for high performance applications
… CMOS circuits. The cascaded CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters, etc.,) is up to 46% less, and performance is improved by 27% than the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, …
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A low power and fast CMOS arithmetic logic unit
… (PTL) based multiplexers and 8 transistors (8T) full adder. Tanner EDA V13 with CMOS technology of 0.25μm is used to design and analyze the circuit. Less number of transistors used will result in small design space area thus reducing the power consumption. The result is being analyzed by …
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Magnetic tunnel junction devices and circuits for in-memory, neuromorphic and radiation hard computing
… in a domain wall-magnetic tunnel junction full adder simulation. Repeatability of writing and resetting the device and an inverter circuit of two devices are also shown in this work. Another promising feature of magnetic tunnel junctions is their intrinsic hardness to radiation, which makes …
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Magnetism and interactions within the single domain limit: reversal, logic and information storage
… more complicated design, two digital binary full adder, was carried out. This novel design provides high stability for logic operation of MQCA and potentially paves way for its application. In addition, the magnetization reversal in perpendicular magnetic anisotropy (PMA) system and its …
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Area-constrained frequency estimation for focal plane arrays
… is combined with the area estimates of a 1-bit full adder (FA) and a 1-bit register in a 65 nm CMOS process to obtain the area costs of the D-DHT and the DFT. Results show that the D-DHT achieves ~2x area reduction over the DFT with no significant impact on detection accuracy. However, D-DHT's …
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Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK
… such as Multiplier–Sorter, Multiplier–Sorter–Adder using the fundamental polymorphic gates, and also analyzes the Power, Performance, and Area (PPA) for these large-scale designs. Similar to the basic and complex polymorphic gates, the functionality of the large-scale polymorphic circuits can …
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Robust and reliable hardware accelerator design through high-level synthesis
… generates architectures consisting entirely of full-adder standard cells; (2) minimum-area modulo adder and subtractor architectures; (3) an array-based modulo multiplier design; and (4) a modulo equality comparator that handles the residue encoding produced by the above. We compare our new …