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Showing 1 to 20 of 27 for “"Frequency synthesizer"”.

  1. A digitally interpolating frequency synthesizer.

    Massachusetts Institute of Technology. Dept. of Electrical Engineering. Thesis. 1973. M.S.

    mit Repository record for A digitally interpolating frequency synthesizer. (opens in a new tab)

  2. A CMOS Frequency Synthesizer for Wireless Sensor Network transceivers

    Negli ultimi anni il mercato dei sistemi wireless è cresciuto immensamente. I sistemi di comunicazione wireless sono penetrati in tutti gli aspetti della nostra vita, dal lavoro al tempo libero, e sono diventati per noi indispensabili. Lo sviluppo di dispositivi a bassissimo consumo di potenza …

    catania Repository record for A CMOS Frequency Synthesizer for Wireless Sensor Network transceivers (opens in a new tab)

  3. A 50 MHz frequency synthesizer with a 1 Hz resolution

    Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.

    mit Repository record for A 50 MHz frequency synthesizer with a 1 Hz resolution (opens in a new tab)

  4. A frequency synthesizer for a 2.4 GHz spread spectrum communications application

    Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.

    mit Repository record for A frequency synthesizer for a 2.4 GHz spread spectrum communications application (opens in a new tab)

  5. A 1.8-Ghz CMOS Fractional -N Frequency Synthesizer With Randomized Multiphase VCO

    … the concept, a fully integrated 1.8-GHz frequency synthesizer with randomized multiphase VCO was designed. The prototype, implemented in a standard 0.6-mum CMOS technology, achieves -118 dBc/Hz phase noise at 1-MHz offset and exhibits close-in phase noise between -80 and -90 dBc/Hz up to …

    uiuc Repository record for A 1.8-Ghz CMOS Fractional -N Frequency Synthesizer With Randomized Multiphase VCO (opens in a new tab)

  6. Frequency synthesis using MEMS piezoelectric resonators

    … this thesis presents two approaches to frequency synthesizer design. The first uses frequency windows of approximately 200 MHz. The 800 MHz to 1 GHz matching network is presented in detail along with predicted performance capabilities across this frequency range. The second design …

    mit Repository record for Frequency synthesis using MEMS piezoelectric resonators (opens in a new tab)

  7. Phase Noise in CMOS Phase-Locked Loop Circuits

    … Phase noise of a CMOS phase-locked loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant …

    lsu-thes Repository record for Phase Noise in CMOS Phase-Locked Loop Circuits (opens in a new tab)

  8. Automatic calibration of modulated fractional-N frequency synthesizers

    … has been the development of a low power, radio frequency transmitter architecture. Specifically, a technique for in service automatic calibration of a modulated phase locked loop (PLL) frequency synthesizer has been developed. Phase/frequency modulation is accomplished by modulating the feedback …

    mit Repository record for Automatic calibration of modulated fractional-N frequency synthesizers (opens in a new tab)

  9. Enabling Blocks for Integrated CMOS UWB Transceivers

    … UWB CMOS single-chip transceivers, namely the frequency synthesizer and the transmission mixer and power amplifier. First we discuss three different models for the simulation of chargepump phase-locked loops, namely the continuous time s-domain and discrete time z-domain approximations and the …

    bologna Repository record for Enabling Blocks for Integrated CMOS UWB Transceivers (opens in a new tab)

  10. Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers

    … a spur reduction method to enhance the overall synthesizer performance, and the oversampling modulator performance is analyzed with the consideration of practical design aspects for frequency synthesizers. A prototype fractional- N frequency synthesizer using a 3-b third-order Delta-Sigma …

    uiuc Repository record for Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers (opens in a new tab)

  11. Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)

    … signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and electronic communication knowledge, and apply them in a practical environment. It does so by providing a …

    uiuc Repository record for Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA) (opens in a new tab)

  12. Performance analysis of VSAT networks

    … technique to use in a VSAT network, since a frequency synthesizer is not required for each terminal. This thesis examines DS-CDMA and SCPC Ku-band VSAT satellite systems for low-density (64 kbps or less) communications. It develops methods for calculating PN coding cross-correlation …

    vt Repository record for Performance analysis of VSAT networks (opens in a new tab)

  13. Compact device modeling and millimeter-wave oscillator design for III-V HBT technology

    … Additionally, tunable clock generator and frequency synthesizer circuits implemented in an indium phosphide (InP) DHBT technology are designed, fabricated, and measured to show the ability of this technology to implement fully integrated sources with moderate power dissipation at …

    uiuc Repository record for Compact device modeling and millimeter-wave oscillator design for III-V HBT technology (opens in a new tab)

  14. Clock multiplication techniques for high-speed I/Os

    Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by …

    uiuc Repository record for Clock multiplication techniques for high-speed I/Os (opens in a new tab)

  15. Tutorial on direct digital synthesizer structure improvements and static timing analysis

    The direct digital frequency synthesizer (DDS) has been widely used in digital communication systems due to its high frequency resolution, fast frequency conversion, and continuous phase change. With the development of microelectronics technology, field-programmable gate array (FPGA) devices have …

    uiuc Repository record for Tutorial on direct digital synthesizer structure improvements and static timing analysis (opens in a new tab)

  16. Frequency and phase locking of a CW magnetron : with a digital phase locked loop using pushing characteristics

    … body of work presented in this thesis is precise frequency and phase control of a 1.2 kW CW cooker magnetron (National 2M137) locked to a 10 MHz reference injected with a very small RF signal (of the order of -40 dBc) creating a suitable RF source for particle accelerators and other sophisticated …

    lancaster Repository record for Frequency and phase locking of a CW magnetron : with a digital phase locked loop using pushing characteristics (opens in a new tab)

  17. Techniques for high-performance digital frequency synthesis and phase control

    … 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. …

    mit Repository record for Techniques for high-performance digital frequency synthesis and phase control (opens in a new tab)

  18. Development of Low-power Wireless Sensor Nodes based on Assembled Nanowire Devices

    … was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for …

    vt Repository record for Development of Low-power Wireless Sensor Nodes based on Assembled Nanowire Devices (opens in a new tab)

  19. Analysis and design of high order digital phase locked loops

    … many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the fact that the feedback loop comparator exhibits …

    maynooth Repository record for Analysis and design of high order digital phase locked loops (opens in a new tab)

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