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Showing 1 to 17 of 17 for “"Fractional-N"”.
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Digital enhancement techniques for fractional-N frequency synthesizers
… In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time …
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Automatic calibration of modulated fractional-N frequency synthesizers
The focus of this research has been the development of a low power, radio frequency transmitter architecture. Specifically, a technique for in service automatic calibration of a modulated phase locked loop (PLL) frequency synthesizer has been developed. Phase/frequency modulation is accomplished by …
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Time-Offset Fractional-N PLLs for Heterodyne FMCW SAR
… an investigation into the use of time-offset fractional-N phase locked loops (PLLs) for heterodyne frequency-modulated continuous-wave (FMCW) synthetic aperture radar (SAR) and the impact of spurii on such a system. Heterodyne receiver architectures avoid phenomena which limit the sensitivity …
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Fractional-N PLL-Based Waveform Synthesis for FMCW SAR
Achieving high-quality transmitted and local oscillator signals is a core objective in the design and implementation of high-resolution radar imaging systems, as the reconstructed images depict the interaction of the signals with elements in the scene. This dissertation concerns optimisation of the …
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Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers
… aspects for frequency synthesizers. A prototype fractional- N frequency synthesizer using a 3-b third-order Delta-Sigma modulator has been designed and implemented in 0.5-gm CMOS. Synthesizing 900 MHz with 1-Hz resolution, it exhibits an in-band phase noise of --92 dBc/Hz at 10-kHz offset with a …
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A 1.8-Ghz CMOS Fractional -N Frequency Synthesizer With Randomized Multiphase VCO
To demonstrate the concept, a fully integrated 1.8-GHz frequency synthesizer with randomized multiphase VCO was designed. The prototype, implemented in a standard 0.6-mum CMOS technology, achieves -118 dBc/Hz phase noise at 1-MHz offset and exhibits close-in phase noise between -80 and -90 dBc/Hz …
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Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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Low phase noise, high bandwidth frequency synthesis techniques
… reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff …
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New strategies for low noise, agile PLL frequency synthesis
… This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are …
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Design Techniques for Frequency Synthesizers in Highly Scaled CMOS Technologies
… will be discussed. Finally, an ultra low noise fractional-N synthesizer will be presented to show how low phase noise fractional-N frequency synthesis can be achieved by taking the full advantage of nano-scale CMOS transistors.
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Clock multiplication techniques for high-speed I/Os
… phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator …
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Energy-efficient wireline transceivers
… detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. …
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Analysis, simulation and design of nonlinear RF circuits
… (DDSM). Both of these circuits are employed in fractional-N frequency synthesizers. Several simulation methods are proposed to capture the locking range of an ILFD, such as the Warped Multi-time Partial Differential Equation (WaMPDE) and the Multiple-Phase-Condition Envelope Following (MPCENV) …
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Extending the Flexibility of an RFIC Transceiver Through Modifications to the External Circuit
… noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in …
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Techniques for high-performance digital frequency synthesis and phase control
… communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations …
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Circuits for time-domain signal processing
… of -242dB is achieved. Finally, a ring-VCO-based fractional-N clock multiplier with optimum threshold TDC (OT-TDC) and two-step quantization noise cancellation is proposed. The proposed PLL allows optimizing the noise performance by increasing the loop bandwidth to filter out the VCO noise while …
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.