Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"Floorplanning"”.
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Performance-driven chip floorplanning and global routing
… algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of …
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Phoenix : an interactive hierarchical topological floorplanning placer
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Physics; and, (B.S.)--Massachusetts Institute of Technology, Dept. of Mathematics, 1985.
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Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
… in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules …
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Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We address the implementation problem using a divide-and-conquer approach. The PATIS …
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Improved Algorithms for High-Level Synthesis and Their Parallel Implementations
… for simultaneous scheduling, binding and floorplanning algorithm are presented. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits, while giving solutions of almost the same or better quality.
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Temperature and Interconnect Aware Unified Physical and High Level Synthesis
… task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to …
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Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its …
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Creative Design Using Collaborative Interactive Genetic Algorithms
… algorithms. I test my model on the problems of floorplanning and the generation of transformations for 3D models. I support collaboration by allowing individual designers to view each others' designs during the evolutionary process and to share designs via case injection. Collaboration causes …
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Automated communication and floorplan-aware hardware/software co-design for SoC
The main objective of modern SoC (system-on-chip) designs is to achieve high-performance while maintaining low power consumption and resource usage. However, achieving such a goal is a difficult and time-consuming engineering task due to the vast design space of hardware accelerators and HW/SW task …