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Showing 1 to 7 of 7 for “"Floating point units"”.

  1. On synthesis and optimization of floating point units

    … level design decisions on the performance, of floating point arithmetic units. By modeling with VHDL and using design synthesis techniques, different architectures of floating point adders, multipliers and multiply-accumulate fused units, are compared using different technologies and cell …

    concordia Repository record for On synthesis and optimization of floating point units (opens in a new tab)

  2. A hierarchical verification of the IEEE-754 table-driven floating-point exponential function using HOL

    The IEEE-754 floating-point standard, used in nearly all floating-point applications, is considered one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task. Most simulation and reachability analysis …

    concordia Repository record for A hierarchical verification of the IEEE-754 table-driven floating-point exponential function using HOL (opens in a new tab)

  3. On low power floating point data path architectures

    … for the implementation of low power floating point units--adders, multipliers and multiply-accumulators. Philosophically, higher level design starts with the characterization of the behavior of the system under consideration. In this work, the design philosophy of floating point …

    concordia Repository record for On low power floating point data path architectures (opens in a new tab)

  4. A statically scheduling compiler for a parameterized numerical accelerator

    … up the numerical accelerator is a collection of floating point units (FPUs) connected to memories through an interconnect structure. The task of the compiler is to create schedules for the interconnect structure and the memories to perform the desired algorithm as fast as possible. The compiler …

    mit Repository record for A statically scheduling compiler for a parameterized numerical accelerator (opens in a new tab)

  5. Design and resource management of reconfigurable multiprocessors for data-parallel applications

    … different types of MPoPCs with hardware FPUs (floating-point units) are designed and implemented for credible performance evaluation and modeling: the coarse-grain MIMD (Multiple-Instruction, Multiple-Data) CG-MPoPC machine based on a processor IP (Intellectual Property) core and the mixed-mode …

    njit Repository record for Design and resource management of reconfigurable multiprocessors for data-parallel applications (opens in a new tab)

  6. Adding limited reconfigurability to superscalar processors

    … of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be …

    epfl Repository record for Adding limited reconfigurability to superscalar processors (opens in a new tab)

  7. Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων

    Οι μονάδες επεξεργασίας δεδομένων αποτελούν τις βασικές δομικές μονάδες όλων των μικροεπεξεργαστών. Κάποια από τα κυκλώματα αυτής της κατηγορίας υλοποιούν τις βασικές αριθμητικές πράξεις πάνω σε δεδομένα τόσο σταθερής όσο και κινητής υποδιαστολής, ενώ κάποια άλλα αναλαμβάνουν την αναδιοργάνωση των …

    patras-thes Repository record for Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων (opens in a new tab)