Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 6 of 6 for “"Floating point unit (FPU)"”.
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Floating-point unit (FPU) designs with nano-electromechanical (NEM) relays
… CMOS despite their slow actuation times. The floating-point unit (FPU) is the most complex arithmetic unit in a computational system. This thesis investigates if the energy-efficiency promise of NEM relays demonstrated before on smaller circuit blocks holds for complex computational structures …
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Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel architectures like Rigel creates new challenges and poses new questions with respect …
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A numerical optimization-based methodology for application robustification: transforming applications for error tolerance
… framework that emulates timing errors in the floating point unit (FPU) of a Leon3 processor. We show that stochastic versions of applications have the potential to produce good quality outputs in the face of timing errors under certain assumptions. We also show that good quality results are …
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Reducing Subthreshold Leakage Power Through Hybrid MOSFET-NEMS Power Gating
… in series with a NEMS switch. Power gating the Floating Point Unit (FPU) of a processor is studied through the use of modern open source computer architecture simulators. Each switch type is used to model power gating to observe energy savings and performance costs. The hybrid power gating model …
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A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing
… structure is integrated into a 32-bit pipelined floating point unit (FPU), implemented in IBM's 90nm technology, and the path delay measurements from 62 copies of the chip are used to analyze die-to-die and within-die variations. The MUX- D-based REBEL is integrated into a pipelined Advanced …
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Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure
… results on within-die path delay variations in a floating-point unit (FPU) fabricated in IBM's 90 nm technology, with 5 pipeline stages, used as a test vehicle in chip experiments carried out at nine different temperature/voltage (TV) corners. Also experimental data has been analyzed for path …