Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 14 of 14 for “"FinFETs"”.
-
High-resolution transmission electron microscopy of III-V FinFETs
… performance. III-V fin field-effect transistors (finFETs) have displayed impressive characteristics but have shown degradation in performance as the fin width is scaled to the sub-10-nm regime. In this work, we use high-resolution transmission electron microscopy (HRTEM) in an effort to understand …
-
Monte Carlo device modeling of 3D n-FinFETs to investigate heat generation
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01
-
Novel Structures for Scalable Vertical Gallium Nitride Power Devices
… enable self-aligned fabrication of vertical GaN finFETs and related devices. Within this work, we also explore the scalability of vertical GaN finFETs. Working with 8-inch GaN substrates, we demonstrate that vertical finFETs can be fabricated using a fully CMOS compatible process flow. This …
-
Development of vertical bulk gallium nitride power devices
… fabrication technologies for vertical power FinFETs. Key processing stesps are refined and demonstrated on large-area devices. The final topic covered is GaN superjunction (SJ) technology in the context vertical power FinFETs. The SJ FinFET concept is first introduced then an underutilized …
-
Insertion of metal oxides into block copolymer nanopatterns as robust etch masks for nanolithography
… for future Fin-field effect transistor (FinFETs) application are detailed.
-
Antimonide-based III-V multigate transistors
… technological challenges for realizing InGaSb FinFETs have been overcome. First, a dry etching technique of heterostructures containing antimonide-based compounds has been developed. Etched fins and vertical nanowires show smooth, vertical sidewalls, high aspect ratio, and compatibility with …
-
Static random-access memory designs based on different FinFET at lower technology node (7nm)
… is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The …
-
Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques
… for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, …
-
Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis
… in planar FETs and triple-gate non-planar FinFETs. (2) to demonstrate whether or not these technologies are viable alternatives to Si and conventional planar FETs. The simulation results indicate that III-V FETs do not outperform Si FETs in the ballistic transport regime, and triple-gate …
-
Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process
… silicon-oninsulator (FD-SOI), Multigate MOSFET, FinFETs, among others, and new design techniques emerge by taking advantage of the improved features of these devices. This thesis focused on the development of analytical expressions for the major performance parameters of the SRAM cache …
-
Modelling and enhancement of the channel mobility of 4H-SiC power MOS devices
… the great inherent potential of the SiC FinFETs, this study provides further impulse to the development of more advanced practical designs that can finally solve the issues which SiC MOS devices face in the channel.
-
Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure
… for GOS defect injection and fault modeling in FinFETs by introducing the defect to a 3D structure of the device for a specific process technology. The behavior of the defective device is captured through simulations in Sentaurus TCAD environment that lead to the generation of more accurate …
-
Design, Modeling and Analysis of Non-classical Field Effect Transistors
… (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device …
-
Performance variations due to layout-dependent stress in VLSI circuits
… owing to the three dimensional nature of the FinFETs, the beneficial stress relaxes along the free-edges of standard cell layouts. Thus, the magnitudes of engineered mechanical stress depend upon the underlying layout topology. To improve circuit performance, a dual gate pitch technique is …