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Showing 1 to 20 of 82 for “"Field Programmable Gate Arrays (FPGAs)"”.

  1. Ein Ansatz für die Nutzung teildefekter Field Programmable Gate Arrays (FPGAs) in der Serienproduktion

    … Eine Alternative bietet die Verwendung von FPGAs. Da die Herstellung von komplett defektfreien FPGAs durch sinkende Strukturgrößen zunehmend schwieriger wird, sind Verfahren erforderlich, mit denen auch leicht defekte FPGAs für eine Serienproduktion eingesetzt werden können. Diese Arbeit …

    oldenburg Repository record for Ein Ansatz für die Nutzung teildefekter Field Programmable Gate Arrays (FPGAs) in der Serienproduktion (opens in a new tab)

  2. Timing-constrained layout algorithms for symmetrical field-programmable gate arrays

    … placement and routing in symmetrical field-programmable gate arrays (FPGAs).

    uiuc Repository record for Timing-constrained layout algorithms for symmetrical field-programmable gate arrays (opens in a new tab)

  3. Timing-driven optimization problems in VLSI CAD

    … where the underlying architecture is regular. Field Programmable Gate Arrays (FPGAs), identical standard cell based architectures and WSI arrays of blocks having a regular structure are the major architectures that are regular. The regularity of these architectures allows us to use powerful …

    uiuc Repository record for Timing-driven optimization problems in VLSI CAD (opens in a new tab)

  4. Hierarchical timing-driven partitioning and placement for symmetrical FPGAs

    Field-programmable gate arrays (FPGAs) allow circuit designers to perform quick prototyping and development. In this thesis we attempt to partition and place a hierarchically described system on multiple FPGA chips so as to minimize the maximum delay through the system. We exploit the given …

    uiuc Repository record for Hierarchical timing-driven partitioning and placement for symmetrical FPGAs (opens in a new tab)

  5. Image Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machine

    … the Image Wavelet Compression (IWC) algorithm on Field Programmable Gate Arrays (FPGAs) by using the run-time reconfigurable custom computing machine design tool Janus. The four routines implementing the IWC are discussed. The structure of Janus is introduced and the IWC implementation design …

    vt Repository record for Image Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machine (opens in a new tab)

  6. Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems

    Modern Field Programmable Gate Arrays (FPGAs) can implement entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. …

    vt Repository record for Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems (opens in a new tab)

  7. Runtime Intellectual Property Protection on Programmable Platforms

    Modern Field-Programmable Gate Arrays (FPGAs) can accommodate complex system-on-chip designs and require extensive intellectual-property (IP) support. However, current IP protection mechanisms in FPGAs are limited, and do not reach beyond whole-design bitstream encryption. This work presents an …

    vt Repository record for Runtime Intellectual Property Protection on Programmable Platforms (opens in a new tab)

  8. Hardware acceleration for sparse Fourier image reconstruction

    … combining general-purpose processors with field-programmable gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical …

    uiuc Repository record for Hardware acceleration for sparse Fourier image reconstruction (opens in a new tab)

  9. Design and implementation of a reconfigurable FPGA-based video frame grabber board

    … processing. The board utilizes two Xilinx field programmable gate arrays (FPGAs) for implementation of different configurations. A software user interface has also been developed to control the operation of the board.

    vt Repository record for Design and implementation of a reconfigurable FPGA-based video frame grabber board (opens in a new tab)

  10. Differential Power Analysis In-Practice for Hardware Implementations of the Keccak Sponge Function

    … and place-and-route when implementing them on Field Programmable Gate Arrays (FPGAs), publish the resulting implementations under the Massachusetts Institute of Technology (MIT) open source license, and show that the resulting implementations demonstrably harden the sponge function against …

    calpoly Repository record for Differential Power Analysis In-Practice for Hardware Implementations of the Keccak Sponge Function (opens in a new tab)

  11. An ECA-Based ZigBee Receiver

    … time and higher computational density than Field Programmable Gate Arrays (FPGAs) with similar computational power. It provides higher computational power than Digital Signal Processors (DSPs) with similar power consumption and price. It also utilizes a library-based graphical development …

    vt Repository record for An ECA-Based ZigBee Receiver (opens in a new tab)

  12. Splash-2 shared-memory architecture for supporting high level language compilers

    … custom computing machine (CCM). CCMs use field programmable gate arrays (FPGAs) as their processing cores, giving them the flexibility of software systems with performance comparable to that of dedicated custom hardware. Hardware description languages are currently used to program CCMs. …

    vt Repository record for Splash-2 shared-memory architecture for supporting high level language compilers (opens in a new tab)

  13. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs

    … acceleration must be done using hardware such as Field Programmable Gate Arrays (FPGAs). Considerable work has been done in academia using FPGAs to accelerate SHAs. These designs were implemented using Hardware Description Language (HDL) based design methodologies, which are tedious and time …

    windsor Repository record for High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs (opens in a new tab)

  14. Improving Field-Programmable Gate Array Scaling Through Wire Emulation

    Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power …

    vt Repository record for Improving Field-Programmable Gate Array Scaling Through Wire Emulation (opens in a new tab)

  15. Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine

    … are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis …

    vt Repository record for Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine (opens in a new tab)

  16. Structured Approach to Dynamic Computing Application Development

    … of research, the dynamic reconfiguration of Field Programmable Gate Arrays (FPGAs) is still very much an art practiced by few. Previous attempts to automate the many low-level details that complicate Run-Time Reconfigurable (RTR) application development suffer severe limitations. This …

    vt Repository record for Structured Approach to Dynamic Computing Application Development (opens in a new tab)

  17. FPGA controlled reconfigurable antenna

    … thesis proposes to utilize the advantages of Field Programmable Gate Arrays (FPGAs) to overcome this dilemma. Two experimental antennas are designed. The first reconfigurable antenna consists of two patches connected by two diodes. The second reconfigurable antenna has sixteen possible …

    unm Repository record for FPGA controlled reconfigurable antenna (opens in a new tab)

  18. Methods for Securing the Integrity of FPGA Configurations

    As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA's configuration, the protection …

    vt Repository record for Methods for Securing the Integrity of FPGA Configurations (opens in a new tab)

  19. A custom computing framework for orientation and photogrammetry

    … when multiple conventional processors and custom gate arrays are inappropriate, due to either excessive cost or risk, a class of devices known as Field-Programmable Gate Arrays (FPGAs) can be employed. FPGAs per the flexibility of a programmable solution and nearly the performance of a custom gate

    mit Repository record for A custom computing framework for orientation and photogrammetry (opens in a new tab)

  20. Implementation of coarse-to-fine visual tracking on a custom computing machine

    … able to detect and follow a moving target in the field of view of a camera. Visual tracking systems have been traditionally developed either as application specific hardware or as software written for parallel architectures because of the large number of computations that have to be performed at …

    vt Repository record for Implementation of coarse-to-fine visual tracking on a custom computing machine (opens in a new tab)

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