Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 45 for “"Fault Model"”.
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An Integrated Circuit Fault Model for Digital Systems
Made available in DSpace on 2014-12-12T20:54:28Z (GMT). No. of bitstreams: 1 7709054.pdf: 4286926 bytes, checksum: 6229d88590171afd9241bf1390525461 (MD5) Previous issue date: 1976
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A Comprehensive Fault Model for Concurrent Error Detection in Mos Circuits
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1984.
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Fail-Safe Testing of Safety-Critical Systems
… systems. It is based on a behavioral and a fault model. The two models are analyzed for compatibility and necessary changes are identified to make them compatible. Then transformation rules are used to transform the fault model into the same model type as the behavioral model. Integration …
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Testing and Error Detection in Iterative Logic Arrays
… considered in the first part of this report. The fault model assumed is that faults in a cell can change a cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. At the array level, two fault-models are considered: in the single cell fault-model (SCFM) we assume …
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High Quality Transition and Small Delay Fault ATPG
… selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture …
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Pacientų žinios ir nuomonė apie jų teisę gauti žalos, padarytos jų sveikatai, atlyginimą /
… Lithuanian residents regarding the compensation model that is applied to patients who suffer health damage while receiving health care services. Scientific literature articles usually discuss the theoretical and practical implementation of the no-fault model in various countries, comparing the …
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A formal model for behavioral test generation
… is presented together with a behavioral VHDL model and a realistic behavioral fault model. Using the behavioral VHDL model, a behavioral VHDL circuit description is represented as a set of equivalent process Statements and connections among them. The behavioral fault model consists of three …
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Issues in Design for Testability and Self-Test
… at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
Fault collapsing, test generation, and fault simulation were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the …
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Reliable processing-in-memory
… metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of …
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COPING WITH DISCREPANCIES OF THE MANUFACTURED WEIGHTS IN THRESHOLD LOGIC GATES
… designed values and significantly affects the fault coverage. A novel fault model for weight defects is proposed. Also an Automatic Test Pattern Generation (ATPG) tool has been implemented that uses the fault model to detect whether the circuit is malfunctioning due to such weight-related …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same …
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A generic fault detection and diagnosis approach for pneumatic and electric driven railway assets
… place the system into an unsafe state. A generic fault detection and diagnosis (FDD) solution for a number of railway assets of different types is therefore desired. In this thesis, five assets, namely the pneumatic train door, point machine and train-stop, the electric point machine and the …
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Distributed Simulation Methods and Algorithms for Superconducting Quantum Computer Reliability
… quantum computers are yet to reach the fault-tolerant regime, and thus the tantalising promises behind quantum algorithms are laid barren. To cross this knowledge-concealing wasteland, one must first understand how both intrinsic and extrinsic noise hinders the reliability of quantum …
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Seismic Site Response and Extraction of Dynamic Soil Behavior From Downhole Array Measurements
… the PSHA-NL procedure to incorporate a finite fault model in PSHA without applying artificial caps on computed ground motions, and include randomized soil column properties representing the Mississippi Embayment to evaluate depth dependent site coefficients. Probabilistic seismic hazard maps …
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The E-algorithm: an automatic test generation algorithm for hardware description languages
… using the VHDL Hardware Description Language. A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, …
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Topics in Totally Self-Checking Circuits and Testable Cmos Circuits
… It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in nMOS, Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are …
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Use of architectural-level primitives in system-level diagnosis and speed up of test vector generation
… such as in CMOS, where the traditional stuck-at fault model is inadequate, and the increase in gate to pin ratio makes it difficult to access and observe the internal signals.
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An efficient test generation algorithm for behavioral descriptions of digital devices
… and concurrent signal assignment statements. The fault model based on previous research includes micro-operation and control faults. The test generation algorithm uses artificial intelligence techniques of goal trees and rule databases and it can make use of human understanding of the device model …
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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
… drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits …
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