Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 46 for “"Fault Coverage"”.
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Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
… that aims to significantly increase the fault coverage in test-per-scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques.
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On fault coverage and fault simulation for multiple signature analysis BIST schemes
Fault coverage and fault simulation issues related to multiple signature analysis (MSA) built-in self-test (BIST) schemes are treated here. A model to predict the fault coverage is presented. Based on this model, the nature of the fault coverage for MSA is discussed. The fault coverage of MSA is a …
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On detection of stuck-open faults using stuck-at test sets in CMOS combinational circuits
The traditional line stuck-at fault model does not properly represent transistor stuck-open (SOP) faults in complementary metal oxide semiconductor (CMOS) circuits. In general, test generation methods for detecting CMOS SOP faults are complex and time consuming due to the sequential behavior of …
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Design for Testability Techniques to Optimize VLSI Test Cost
… of test data volume reduction depends on the fault coverage achievable in the broadcast mode. However, the fault coverage achieved in the broadcast mode of ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the …
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ATPG and DFT Algorithms for Delay Fault Testing
… and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based …
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A built-in self-test PLA generator
… PLA design is known to be effective in area and fault coverage. We modified the original design (which is presented for nMOS PLAs) for CMOS PLAs and added the control circuit. Implementation of BPG was based on MPLA, a PLA generator. Tiles necessary for BIST PLAs were created and added to the …
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A tool for reliability analysis of electrical power systems
… and incorporates the concept of fault coverage, which is the probability that, given a fault has occurred, the system remains operational within some acceptable performance requirements. The tool’s computational engine automatically builds a Markov reliability model of the system …
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METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS
… sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same …
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Digital core output test data compression architecture based on switching theory concepts: Model implementation and analysis
… module under test (MUT), while maintaining the fault coverage information. The suggested techniques take advantage of some well known concepts of conventional switching theory, particularly those of cover table and frequency ordering as commonly utilized in the minimization of switching …
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Space compactor design for built-in self-testing of VLSI circuits from compact test sets using sequence characterization and failure probabilities.
… the circuit under test (CUT) while maintaining fault coverage information is presented in this dissertation. The compaction technique utilizes the concepts of the Hamming distance and sequence weight, together with the use of failure probabilities of the errors in the selection of specific gates …
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High Quality Test Generation at the Register Transfer Level
… tests as well as providing high levels of fault coverage during structural test, typically outperforming previous state of the art methods. First, a semi-formal method for functional verification is presented. The approach utilizes a SMT-based bounded model checker in combination with an …
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On the Computation of LFSR Characteristic Polynomials for One-Dimensional and Two-Dimensional Test Pattern Generation
… the test pattern computation and the fault coverage are constrained to the preselected architecture. Work has been done to determine desirable characteristics in the LFSR to be used. Also, work has been done in the use of these predefined architectures, in order to compact the test …
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Integrated Enhancement of Testability and Diagnosability for Digital Circuits
… used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish …
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
… volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate external test equipment, enables the application of a …
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High Quality Transition and Small Delay Fault ATPG
… selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture …
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High-Level Testability Analysis and Enhancement for Digital Systems
… partial-scan implementations that achieve better fault coverage compared to conventional gate-level selection techniques.
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Techniques for sequential circuit automatic test generation
… automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a …
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Online Techniques for Enhancing the Diagnosis of Digital Circuits
… most of these activities cater for all possible faults without making any assumptions about the actual defects present in the circuit. As the size of the circuits continues to increase (following the Moore's Law) the size of the test sets is also increasing exponentially. It follows that the cost …
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Feedback Based Performance Management and Fault Tolerance for Networked and Embedded Computing Systems
… exploit the use of feedback control to achieve fault tolerance for real-time embedded control systems. We propose ORTGA (On-demand Real-Time GuArd), a new fault tolerance architecture which utilizes feedback control based software execution. ORTGA delivers the same functionalities as previously …
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