Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 290 for “"FPGAs"”.
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Split learning on FPGAs
… reflects a broader trend in the increased use of FPGAs in sensor systems in order to reduce size and power consumption without a corresponding loss in performance or flexibility. At the same time, the field of machine learning is diversifying to include distributed deep learning methods like split …
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Framework for Hardware Agility on FPGAs
As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational …
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Open-Source Bitstream Generation for FPGAs
… limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work.
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Educational applications of partial reconfiguration of FPGAS
… systems such as Field Programming Gate Arrays (FPGAs) has gained a lot of attention during the past ten years. Recently, Xilinx has released the first commercially available PR implementation for its FPGAs. However, there is a lack of educational tools for PR instruction. In addition, the design …
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Partitioning a given circuit targeting multiple Fpgas
… design (represented as a hypergraph) into Multi-FPGAs uses a bi-level approach by initially clustering the design and then applying the bipartitioning technique iteratively. Each partition generated by the iterative bipartitioning technique should meet the constraints given by the FPGAs …
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SEU-Induced Persistent Error Propagation in FPGAs
This thesis introduces a new way to characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section …
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Fast place and route approaches for FPGAs
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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Evaluation Techniques for Mapping IPs on FPGAs
The phenomenal density growth in semiconductors has resulted in the availability of billions of transistors on a single die. The time-to-design is shrinking continuously due to aggressive competition. Also, the integration of many discrete components on a single chip is growing at a rapid pace. …
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BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs
With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform …
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High-Level CSP Model Compiler for FPGAs
The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of …
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A combined clustering and placement algorithm for FPGAs
… such as field-programmable gate arrays (FPGAs), is an inherent speed disadvantage over ASIC technologies. To mitigate this speed disadvantage, this thesis presents a novel algorithm to improve timing performance at the possible expense of area and runtime. The algorithm presented …
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Nimblock 2.0: Serverless computing with multi-tenant FPGAS
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-05-01
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HAsim : cycle-accurate multicore performance models on FPGAs
… modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with …
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Cycle-accurate modeling of multicore processors on FPGAs
We present a novel modeling methodology which enables the generation of a high-performance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on …
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Efficient arithmetic for high speed DSP implementation on FPGAs
The author was sponsored by EnTegra Ltd, a company who develop hardware and software products and services for the real time implementation of DSP and RF systems. The field programmable gate array (FPGA) is being used increasingly in the field of DSP. This is due to the fact that the parallel …
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Integrating Biological and Artificial Neural Networks Processing on FPGAs
Neural interfaces are rapidly gaining momentum in the current landscape of neuroscience and bioengineering. This is due to a) unprecedented technology capable of sensing biological neural network electrical activity b) increasingly accurate analytical models usable to represent and understand …
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Throughput Constrained and Area Optimized Dataflow Synthesis for FPGAs
Although high-level synthesis has been researched for many years, synthesizing minimum hardware implementations under a throughput constraint for computationally intensive algorithms remains a challenge. In this thesis, three important techniques are studied carefully and applied in an integrated …
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Hierarchical timing-driven partitioning and placement for symmetrical FPGAs
Field-programmable gate arrays (FPGAs) allow circuit designers to perform quick prototyping and development. In this thesis we attempt to partition and place a hierarchically described system on multiple FPGA chips so as to minimize the maximum delay through the system. We exploit the given …
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