Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 69 for “"FLOPS"”.
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Selection of flip-flops for partial scan design
… sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a …
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A low-speed analogue for analysis of flip-flops
Thesis (M.S.) Massachusetts Institute of Technology. Dept. of Electrical Engineering, 1949.
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Selection of flip-flops for partial scan paths by use of a statistical testability measure
… that a partial scan path include only those flip-flops that provide the greatest improvements in circuit testability. STAFFS, a tool that identifies such flip-flops, has been developed. It uses a statistical testability measure to acquire quantitative data for the controllabilities and …
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Pac-man shaped magnetic tunnel junctions for SEU-resistant CMOS-based magnetic flip flops for space applications
… are proposed for CMOS-based magnetic flip flops for space applications. Micromagnetic simulation was performed on single layer elongated Pac-man shape, modified rectangular shape, and square shaped bilayer for magnetization process. The experimental effect of CoFe and IrMn thickness on the …
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Developing a multi-level fault injection environment
… stuck-at faults. Interestingly only a few of the flops which are affected by radiation cause soft errors, due to different propagation paths and functional impact of the flops. In order to improve the dependability of a system with reasonable overhead, the flops in a design which are most …
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Probability of latching single event upset errors in VLSI circuits
… on the effect of transient faults on flip-flops rather than combinational logic. This is due to several reasons. First, transient faults, also known as Single Event Upsets (SEU), were first observed in memory circuits located on board satellites. Second, an SEU can leave a lasting effect on …
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DYNAMIC NEURAL NETWORKS FOR EFFICIENT VISION MODEL INFERENCE
… with negligible trainable parameters, reducing FLOPs by 30% while significantly lowering training costs. Diffusion Transformers (DiT) Acceleration: We introduce a dynamic architecture for visual generation, achieving a 50% FLOPs reduction and 1.7× speedup with improved quality. Vision-Language …
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PARAMETERS THAT AFFECT PARALLEL PROCESSING FOR COMPUTATIONAL ELECTROMAGNETIC SIMULATION CODES ON HIGH PERFORMANCE COMPUTING CLUSTERS
… metric was FLoting-point Operations Per Seconds (FLOPS) which indicates system performance for scientific applications that make heavy use of floating-point calculations. Is FLOPS an effective metric for parallelized CEM simulation tools on new multicore system? Parallel CEM software needs to be …
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Adiabatic Approach for Low-Power Passive Near Field Communication Systems
… power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of …
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Development of a Multi-Disciplinary Design Optimization Framework for a Strut-Braced Wing Transport Aircraft in PACELAB APD 3.1
… to results for the same mission generated with FLOPS and VT MDO are also discussed. For the strut-braced configuration, large fuel savings on the order of 37% over the baseline 737-800 aircraft are predicted, while for the cantilever aircraft savings of 10-30% are predicted depending on whether …
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Reducing Global Memory Accesses in DNN Training using Structured Weight Masking
… accuracy, theoretical computational cost (FLOPs), and theoretical memory movement. Results indicate that model accuracy remains robust up to approximately 50% sparsity when the mask is also applied during the backward pass; beyond this threshold, classification accuracy degradation is …
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A low phase noise ring oscillator phase-locked loop for wireless applications
… based on modified true single-phase clock flip-flops with integrated logic. A fully differential charge pump with switched-capacitor common mode feedback is utilized in conjunction with a nonlinear phase-frequency detector for accelerated acquisition time.
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Use of High-Level Descriptions in Fault Simulation and Test Generation
… as compared with low-level gates and flip-flops which are used in conventional approaches, and the number of primitives elements in a circuit can be significantly reduced. This reduces the computation needed for fault simulation and test generation. In many instances, functional …
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Techniques for communication optimization of parallel programs in an adaptive runtime system
… achievable floating point operations per second (FLOPs), relative to earlier generations with a corresponding increase in network bandwidth or sufficient decrease in latency. This unequal increase has previously partially been addressed by partitioning duties between runtimes at the shared memory …
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High Temperature CMOS Silicon Carbide Asynchronous Circuit Design
… hold times of clocked components, such as D-Flip Flops, of a traditional synchronous digital circuit. Focusing primarily on high temperature circuit operation, this dissertation presents a digital circuit design methodology pairing an asynchronous circuit design paradigm called NULL Convention …
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Low-Complexity Structured Neural Networks and Their Usage in Image and Signal Processing
… of the DST. This network achieves the lowest FLOPs at 0.02399 G and the least number of parameters at 6.75M com- pared to other benchmarked networks, including CNN, R-CNN, Faster R-CNN, EfficientNet- B0, and ViT-B/16 on the STL-10 dataset at 128 × 128 resolution, marking a reduction of at …
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Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug
… computation, efficient ordering of trace flip-flops and alternate vector reversal that reduces the entropy of the trace data, making them more amenable for compression. The order of the trace flip-flops is computed off-chip using a probabilistic algorithm. The difference vector computation and …
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BETA: Behavioral Testability Analyzer and its applications to high-level test generation and synthesis for testability
… used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach called Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also …
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Efficient VLSI Implementation of Arithmetic Units and Logic Circuits
… distribution and undesired activity of flip-flops due to presence of clocks. The second contribution of the dissertation is the power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The …
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The Role of Constraints and Vehicle Concepts in Transport Design: A Comparison of Cantilever and Strut-Braced Wing Airplane Concepts
… from NASA Langley's Flight Optimization System (FLOPS) was replaced by LMAS proprietary equations. A detailed study on the impact of the equations from LMAS on the four designs was done, comparing them to the designs that used the FLOPS equations. Results showed that there was little difference …
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