Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"Energy delay product"”.
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The SCALE DRAM subsystem
… an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but introduce a performance penalty. This thesis …
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Three-dimensional device and circuit architectures : new systems with new nanotechnologies
… been a major driving force to improve computing energy efficiency (quantified by the energy-delay product, EDP, the product of energy consumption and circuit delay) for decades. However, continued silicon scaling is becoming increasingly challenging. This is motivating the search for …
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Carbon Nanotubes for Space Electronics: Enabling New Applications with Emerging Technologies
… projected to provide orders of magnitude energy-delay-product (EDP) improvement versus conventional silicon-based digital VLSI systems. I experimentally demonstrate new three-dimensional (3D) device and circuit architectures leveraging unique low temperature processing of CNTs, demonstrate …
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On synthesis and optimization of floating point units
… works have been proposed to minimize the energy delay product with special emphasis on power reduction. A new low power, high performance, transition activity scaled, double data path floating point multiplier has been proposed and its validity is proved by comparing it to a single data …
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Reliable spin-based computing systems
… and have the potential to beat the energy-delay product of CMOS. However, thermal noise in these devices makes their switching delay a random variable. Deterministic von Neumann style computing requires them to operate at worst case delay (and low error-rate), thereby completely …
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Systematic Modeling and Design of Sparse Deep Neural Network Accelerators
… HighLight achieves a geomean of upto 6.4× better energy-delay product (EDP) across workloads with diverse sparsity degrees, and always sits on the EDP-accuracy Pareto frontier for representative DNNs.
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Cross-layer methods for energy-efficient inference using in-memory architectures
… such as DNNs under stringent constraints on energy, latency, and form-factor is a formidable challenge. In conventional von Neumann architectures, the energy and latency cost of realizing ML algorithms is dominated by memory accesses. To address this issue, the deep in-memory architecture …
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Imperfection-Aware Design of CNFET Digital VLSI Circuits
… characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that …
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Towards Secure Machine Learning Acceleration: Threats and Defenses Across Algorithms, Architecture, and Circuits
… largely focus on improving the throughput, energy-efficiency, and area-efficiency, while the hardware-level security solutions are significantly less well understood. This thesis investigates the memory security for DNN accelerators, where the off-chip main memory cannot be trusted. The …
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A comparative study of the effects of parallelization on ARM and Intel based platforms
… and manufacturers to develop powerful yet energy efficient processors. Increasing the parallelism available in the hardware has proven to be a great way to maintain and even improve performance while sustaining a manageable power budget. Specialized hardware such as graphics processing …
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Power Analysis and Prediction for Heterogeneous Computation
… systems with respect to power, performance and energy characteristics with the end use applications. Additionally, the chosen systems must often achieve performance objectives without exceeding their respective power budgets, a task that is usually borne by a software-based power management …
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Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability
… computing applications, a majority of system energy is consumed moving data between compute and off-chip memory, which are often physically separate with limited connectivity. This is termed the “memory wall”. A promising solution to this problem is monolithic 3D integration, in which layers …
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Energy efficient computing : from nanotubes to negative capacitance
… been a major driving force to improve computing energy efficiency (quantified by the energy-delay product, EDP, the product of energy consumption and circuit delay) for decades. However, continued silicon scaling is becoming increasingly challenging. This is motivating the search for …
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Power and performance optimization of negative capacitance transistor circuits
… capacitance at low gate voltages. The effective delay is determined by the ratio of the gate capacitance and drain current (t = Q/I) at the operating voltage of interest. NCFETs exhibiting high drain current operate faster at low voltages. As voltage increases, the NCFETs with less abrupt …
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Computing with Spintronics: Circuits and architectures
… proposed design achieves 1.5X-4X improvements in energy-delay product compared to a CMOS baseline. 2) It describes the first attempt to use DWM in the cache hierarchy of general-purpose processors. DWM promises unparalleled density by packing several bits of data into each bit-cell. TapeCache, the …
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Deep in-memory computing
… machine learning (ML) algorithms under stringent energy constraints with battery-powered electronics. Especially, energy consumption in memory subsystems dominates such a system's energy efficiency. In addition, the memory access latency is a major bottleneck for overall system throughput. To …
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AB initio study and design of 2D materials/III-nitrides-based post-CMOS devices using first-principles multiphysics simulation framework
… substituting Mo to achieve negative formation energy values with impurity states all sitting at less than 0.1 eV from the valence band maximum (VBM), making them the optimal p-type dopant candidates. Moreover, our 5x5 cell model shows that B, a group III element, can induce impurity states very …
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Popcorn Linux: A Compiler and Runtime for Execution Migration Between Heterogeneous-ISA Architectures
… computing in order to achieve better performance energy efficiency for heavy computational tasks. Although heterogeneity adds significant complexity to both hardware and software, recent works have shown tremendous power and performance benefits obtainable through specialization. It is clear that …
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Self-tuning dynamic voltage scaling techniques for processor design
… be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving …