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Showing 1 to 3 of 3 for “"Embedded Test Structure"”.

  1. A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing

    … of path delays is best carried out using embedded techniques applied to actual product macros, as opposed to scribe line test structures or embedded ring oscillators (RO). In addition to characterizing performance, such delay measurement techniques can be used to improve model-to-hardware …

    unm Repository record for A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing (opens in a new tab)

  2. Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure

    … increasingly sensitivity to design-context. Embedded test structures (ETS) continue to play an important role in the development of models of PVs and as a mechanism to improve correlations between hardware and models. Variations in path delays are increasing with scaling, and are increasingly …

    unm Repository record for Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure (opens in a new tab)

  3. DETECTING DELAY ANOMALIES INTRODUCED BY HARDWARE TROJANS USING CHIP AVERAGING AND AN ON-CHIP HIGH RESOLUTION EMBEDDED TEST STRUCTURE

    … are measured using a high resolution on-chip embedded test structure called a time-to-digital converter (TDC) that provides approx. 25 ps of timing resolution. A calibration method for the TDC as well as a chip-averaging technique are demonstrated to nearly eliminate chip-to-chip and …

    unm Repository record for DETECTING DELAY ANOMALIES INTRODUCED BY HARDWARE TROJANS USING CHIP AVERAGING AND AN ON-CHIP HIGH RESOLUTION EMBEDDED TEST STRUCTURE (opens in a new tab)