Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"Dynamic random access memory"”.
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Chemically modified Ta₂O₅ thin films for dynamic random access memory (DRAM) applications
… the fabrication of a reliable high-density memory device. In the present work, the effects of Al addition on Ta₂O₅ thin films were systematically studied. The structural and electrical properties of these chemically modified thin films were investigated in detail to establish their potential …
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The SCALE DRAM subsystem
Dynamic Random Access Memory (DRAM) is consuming an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but …
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Low-Temperature Chemical Vapor Deposition of Ruthenium and Manganese Nitride Thin Films
… intended for use in interconnects and in dynamic random access memory electrodes, a known material for use in microelectronics but for which a more conformal, yet fast process than previously demonstrated is required. The other is manganese nitride, which could be used as active magnetic …
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A strategic and financial analysis of the DRAM industry
The manufacturing and development of Dynamic Random Access Memory (DRAM) is a large global industry that involves various advanced technologies and significant capital expenditures. The industry has seen tremendous developments over the past few decades allowing for rapidly improving product …
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Characterizing Retention behavior of DDR4 SoDIMM
… factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. …
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Software-defined Significance-Driven Computing
… it to operate seamlessly on top of unreliable memory and provide a<br/>user-space interface for memory allocation from the unreliable portion of the physical memory. Having this framework in place<br/>allowed us to identify what we call the refresh-by-access property of applications that use …
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EPITAXIAL SPIN-ORBIT AND MAGNETIC MATERIALS FOR INTEGRATION ONTO A SEMICONDUCTOR PLATFORM
… historically served as the backbone fordigital memory storage. In recent times, however, charge-based memories, such as flash and dynamic random access memory (DRAM), have become more commonplace. Over the last few decades, advancements in the field of spintronics, which aims to unify usage of …
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Configuring In-Memory Caches: From TTL-Aware Sizing to Interval-Based Historical Analysis with HistoChron
In-memory caches such as Memcached and Redis are crucial for enhancing the performance of distributed systems by significantly reducing query response times. Correctly sizing these caches is critical, especially considering that prominent organizations use terabytes to petabytes of Dynamic Random …
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High performance digital signal processing: Theory, design, and applications in finance
… processing units is improved such that the access to the dynamic random access memory is entirely coalesced. The speed is improved by a factor of 68.5 by the proposed method compared to a CPU implementation for a square matrix of size 1,024. Third, several tools developed and implemented in …
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Refresh reduction in dynamic memories
… DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies experience higher temperatures. Elevated …
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Impact of Lot Dedication on the Performance of the Fab
… manufacturing line that is used to produce four dynamic random access memory (DRAM) products, requiring approximately 240 stages with 18 photolithography layers, is considered. The problem we propose to investigate can concisely be described as follows: Given a set of products to be processed in …
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, …
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Hochauflösende Rutherford-Streuspektrometrie zur Untersuchung von ZrO2-Schichtwachstum im Anfangsstadium
Die vorliegende Arbeit entstand im Rahmen einer Kooperation des Forschungszentrums Dresden-Rossendorf mit Qimonda Dresden GmbH & Co. OHG. Mithilfe der hochauflösenden Rutherford-Streuspektrometrie (HR-RBS) wurden das Diffusionsverhalten und Schichtwachstum von ZrO2 auf SiO2 und TiN im …
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Next-generation safety-critical systems on multi-core platforms
… Shared hardware resources like caches, main memory, and I/O buses are all sources of unpredictable timing behavior and temporal dependencies among real-time tasks running in parallel. As a result, certifying systems deployed using multi-core platforms is significantly more challenging …