Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 13 of 13 for “"Digital Phase-locked Loop"”.
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FPGA-based digital phase-locked loop analysis and implementation
The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to …
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Clock synthesizer design with analog and digital phase locked loop
… clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The all-digital counterpart of the analog PLL will also be presented for its ultra low power and small …
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A new programmable low noise all digital phase-locked loop architecture
… today almost without exception there are phase-locked loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented …
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Design of all digital phase-locked loop in serial link communication
… speed links, clocking circuitry is vital, and phase-locked loop (PLL) is at the heart of every on-chip clocking circuit. The clocking circuitry needs to be robust, low-power and fast in order to fulfill the increasing demand for high data rate links. The performance of the input/output (I/O) …
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A digital phase-locked loop for hard disk drive read channel appliations
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
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Frequency and phase locking of a CW magnetron : with a digital phase locked loop using pushing characteristics
… in this thesis is precise frequency and phase control of a 1.2 kW CW cooker magnetron (National 2M137) locked to a 10 MHz reference injected with a very small RF signal (of the order of -40 dBc) creating a suitable RF source for particle accelerators and other sophisticated applications. …
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Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources
… for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of …
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Fast all-digital carrier synchronization techniques for linear modulation formats
… studies fast, independent, low complexity, all-digital data-aided (DA) feedforward (FF) and decision-directed (DD) feedback (FB) carrier recovery (CR) techniques based on oversampling, suitable for linear modulation schemes ( M -ary phaseshift-keying ( M -PSK) and M -ary quadrature amplitude …
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Viability study to implement peak load shaving at UCT Medical School
… It was purposed that implementing a three-phase inverter in conjunction with a lead-acid battery at UCTMS for PLS is technical and financial viable. Five-year UCTMS MMD data history was gathered from UCT maintenance office as well as eight-month UCTMS load profile, which was gathered using …
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Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system
The performance of phase synchronization and code tracking of a digital phase-locked loop (PLL) and delay-locked loop (DLL), respectively, is investigated in wideband asynchronous multirate DS-CDMA system. Dynamic Partial Correlation (DPC) method is proposed to evaluate the autocorrelation and its …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected …
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Nanoscale SoC-kompatibler FM-Radio Transmitter auf Basis einer vollständig digitalen PLL
… However, music is now increasingly available in digital form as an MP3 file, e. g. on a phone as a mobile media player. As a result, an interface between the mobile phone as music player and the classic radio as a playback device is usually missing. The aim of this study is the implementation of …
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Digital enhancement techniques for fractional-N frequency synthesizers
… levels. In the first part of this work, a digital fractional-N phase locked loop (FNPLL) that employs a high resolution time-to-digital converter (TDC) and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a …