Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Design-technology co-optimization"”.
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Design-technology co-optimization in next generation lithography
Lithography continues to be the backbone of the integrated circuit (IC) industry. While the critical dimension (CD) keeps shrinking with the pace of Moore’s law, the progress in lithography lags far behind. The gap between manufacturing capability and the expectation of design performance finally …
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Design-technology Co-optimization for Sub-2 nm Technology Node Based on 2D Materials
… such as Artificial Intelligence (AI) and 6G communications have driven stringent demands for hardware components that enable faster and more energy-efficient computation. With the diminishing returns of traditional silicon-based scaling and the escalating complexity of advanced semiconductor …
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System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials
Over the past 60 years, the semiconductor industry has focused on developing highly scaled electronic devices and high-density integrated circuits. However, bottlenecks have arisen recently as transistor dimensions approach the physical limits, and integration density is constrained. This thesis …
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Optically Controlled Vertical GaN finFET for Power Applications
… with high voltage and current capabilities become crucial in many applications. However, current power devices are mostly electrically triggered. Multilevel converters made of such devices often require complicated gate-driving circuits and are susceptible to electromagnetic interference …
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Static random-access memory designs based on different FinFET at lower technology node (7nm)
… to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells …
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Design automation algorithms for advanced lithography
In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with Moore's law, different kinds of advanced lithography have been proposed, such as multiple patterning lithography (MPL), …
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Optimization for advanced lithography
… circuit (IC) fabrication. Below the 28 nm technology node, conventional 193 nm immersion lithography (193i) with single exposure has reached its printability limit. In order to keep up with Moore's law, a lot of advanced lithography and process techniques have been coming up in the recent …