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Showing 1 to 5 of 5 for “"Design-Technology Co-Optimization (DTCO)"”.

  1. System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials

    Over the past 60 years, the semiconductor industry has focused on developing highly scaled electronic devices and high-density integrated circuits. However, bottlenecks have arisen recently as transistor dimensions approach the physical limits, and integration density is constrained. This thesis …

    mit Repository record for System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials (opens in a new tab)

  2. Optically Controlled Vertical GaN finFET for Power Applications

    … with high voltage and current capabilities become crucial in many applications. However, current power devices are mostly electrically triggered. Multilevel converters made of such devices often require complicated gate-driving circuits and are susceptible to electromagnetic interference …

    mit Repository record for Optically Controlled Vertical GaN finFET for Power Applications (opens in a new tab)

  3. Design-technology Co-optimization for Sub-2 nm Technology Node Based on 2D Materials

    … such as Artificial Intelligence (AI) and 6G communications have driven stringent demands for hardware components that enable faster and more energy-efficient computation. With the diminishing returns of traditional silicon-based scaling and the escalating complexity of advanced semiconductor …

    mit Repository record for Design-technology Co-optimization for Sub-2 nm Technology Node Based on 2D Materials (opens in a new tab)

  4. Design-technology co-optimization in next generation lithography

    Lithography continues to be the backbone of the integrated circuit (IC) industry. While the critical dimension (CD) keeps shrinking with the pace of Moore’s law, the progress in lithography lags far behind. The gap between manufacturing capability and the expectation of design performance finally …

    uiuc Repository record for Design-technology co-optimization in next generation lithography (opens in a new tab)

  5. Optimization for advanced lithography

    … circuit (IC) fabrication. Below the 28 nm technology node, conventional 193 nm immersion lithography (193i) with single exposure has reached its printability limit. In order to keep up with Moore's law, a lot of advanced lithography and process techniques have been coming up in the recent …

    uiuc Repository record for Optimization for advanced lithography (opens in a new tab)