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Showing 1 to 14 of 14 for “"Design for test"”.
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A Design for Test and Security Methodology for Integrated Circuits
… Many companies have outsourced their need for IC fabrication to eliminate the overhead costs associated with operating a fabrication facility. While outsourcing has its benefits, it provides opportunities for hardware Trojan (HT) injection at different design levels. Hardware Trojans and IP …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous …
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Techniques for sequential circuit automatic test generation
Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a …
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A predictive troubleshooting model for early engagement
… Card Assembly, the department responsible for the production of circuit card assemblies from across all of Raytheon's businesses. Circuit Card Assembly includes manufacturing, test, quality, finance and other groups, functioning as its own business within Raytheon IDS. Circuit Card Assembly …
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Hardware implementation of a low-power two-dimensional discrete cosine transform
… dedicated, two-dimensional, Discrete Cosine Transform (DCT) core meeting all IBM Softcore requirements is developed. Power is optimized completely at the algorithmic, architectural, and logic levels. The architecture uses row-column decomposition of a fast 1-D algorithm implemented with …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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Testing of delay-insensitive circuits using protocol extraction strategies
… believed that purely DI circuits are easy to test because any fault will prevent the generation of an acknowledge signal. We show that this is not always true under a general set of components. A Petri net fault model is used to reveal the possibility of critical races/hazards during test. A …
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Optimization Techniques for Performance and Power Dissipation in Test and Validation
The high cost of chip testing makes testability an important aspect of any chip design. Two important testability considerations are addressed namely, the power consumption and test quality. The power consumption during shift is reduced by efficiently adding control logic to the design. Test …
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Design for pre-bond testability in 3D integrated circuits
… that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is …
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METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS
Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear …
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Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test
… system-on-chip (SoC) or System-on-Package (SoP) design has been increasingly important in cost-effective manufacturing test for mixed-signal devices. A typical SoP encapsulates many of its internal functions, and its production test is performed by application of test signals to the SoP under …
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Test and diagnosis of resistive bridges in multi-Vdd designs
A key design constraint of circuits used in hand-held devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques aim to increase the battery life by adjusting the supply voltage (Vdd) and operating frequency, according to the workload. …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
… alleviate many of these problems, and is therefore viewed as a promising interconnect paradigm of the future. In addition, NOC building blocks consist of reusable components and require minimal design effort in building a large and complex system. In addition to NOCs, 3D integration technology …