Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 111 for “"Design Flow"”.
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Python based FPGA design-flow
… As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER …
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A Management Paradigm for FPGA Design Flow Acceleration
… tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that …
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A Design Flow for Additively Manufactured 3D Metasurface Antennas
… of the antenna. Due to this, the process of designing and developing a MTS antenna can be intensive in terms of both the time to understand the how these antennas operate and time running calculations that achieve optimal performance. Through the use of automation for geometry creation in …
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New Methodology for the Estimation of StreamVane Design Flow Profiles
… which is considered a type of non-uniform inflow inlet distortion, is characterized by the presence of swirling flow in an inlet. The presence of swirling flow entering an engine can affect the compression systems performance and operability, therefore it is an area of current research. A …
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FOpenCL: An optimized OpenCL-to-FPGA design flow for Xilinx SDx
… work, we discover and explain why OpenCL kernels designed for GPU will have poor performance on FPGA if the kernels are copied over without transformation and optimization. Specifically, we uncover an implicit limitation in Xilinx SDx, which claims to support OpenCL. Then, we explore the …
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Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool
… components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth …
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3-D flow and performance of a rocket pump inducer at design and off-design flow rates
… a 3-D Navier-Stokes solver, The Moore Elliptic Flow Program. Design and off-design flow rates were simulated to qualitatively and quantitatively study the effects of flow rate on the flow and performance. Several views of the results were created to aid flow visualization. The 3-D laser …
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Experimental and numerical investigations of the off-design flow physics in a supersonic through-flow fan cascade
… and 4.8 x 10⁶, respectively. In addition to mean flow measurements, Reynolds normal and shear stresses were measured as functions of cascade incidence angle and streamwise location in the near-wake and the far-wake. The extremities of profiles of both the mean and turbulent wake properties were …
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Secondary flows in centrifugal compresser impellers
Detailed flow measurements made in a 1 metre diameter, shrouded, centrifugal (Ghost) impeller running at 500 rpm are presented. Relative velocities and rotary stagnation pressures $(p*=p-\frac{1}{2}\ρω^{2}r^{2}+\frac{1}{2}\ρW^{2})$ were measured on five cross-sectional planes between the impeller …
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Comparison of high level design methodologies for algorithmic IPs : Bluespec and C-based synthesis
High level hardware design of Digital Signal Processing algorithms is an important design problem for decreasing design time and allowing more algorithmic exploration. Bluespec is a Hardware Design Language (HDL) that allows designers to express intended microarchitecture through high-level …
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Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which …
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Automatic generation of an LC voltage controlled oscillator
… receivers, and clock generators. A typical design flow for a VCO involves architecture selection based on specification, calculation of circuit parameters, simulation, and iterations of circuit parameters based on the simulation result. In such a design flow, changes in specification or …
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Silicon Germanium SRAM and ROM Designs for Wide Temperature Range Space Applications
<p>This thesis presents a design flow from specifications and feature requirements to embeddable blocks of SRAM and ROM designs from 64 bytes to 1 kilobyte that are suitable for lunar environments. The design uses the IBM SiGe 5AM BiCMOS 0.5 micron process for a synchronous memory system capable of …
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Energy-aware architectures, circuits and CAD for field programmable gate arrays
… fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the …
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Circuit design for logic automata
… extensible, clockless structure, we designed an ALA cell library in 90 nm CMOS technology and established a "pick-and-place" design flow for fast ALA circuit layout. The work flow gracefully aligns the description of computer programs and circuit realizations, providing a simpler and …
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Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development
Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers …
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Anticipating system-level electromagnetic interference using numerical methods and measurement techniques
… concurrent module-level and vehicle-level EMC design flow at early development stages is becoming important and inevitable for solving the accompanying increase of electromagnetic interference (EMI) problems. In this work, strategies combining both numerical modeling and experimental techniques …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… silicon substrates of the chip and uses liquid flow to remove heat inside the chip, is an effective active cooling scheme for 3D-ICs. While the micro-fluidic cooling provides excellent cooling to 3D-ICs, the associated overhead (cooling power consumed by the pump to inject the coolant through …
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Modern VLSI Placement Observing Technology Constraints
The placement process is a key step in physical design as it directly impacts circuit performance, area, power consumption, reliability, and the quality of other steps, such as routing, in the physical design flow. The placement problem has become ever more complex and challenging due to a wide …
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Formal Approaches to Globally Asynchronous and Locally Synchronous Design
… by two trends in the system-on-chip (SoC) design industry. First, due to the incessant technology scaling, the interconnect delays are getting larger compared to gate delays, leading to multi-cycle delays in communication between functional blocks on the chip, which makes implementing a …
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