Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 16 of 16 for “"Delay-locked loop"”.
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A delay-locked loop for clock recovery and data synchronization
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.
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Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system
… and code tracking of a digital phase-locked loop (PLL) and delay-locked loop (DLL), respectively, is investigated in wideband asynchronous multirate DS-CDMA system. Dynamic Partial Correlation (DPC) method is proposed to evaluate the autocorrelation and its power spectrum density (PSD) …
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Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
Delay-locked loop (DLL)-based clock multipliers have several inherent advantages over conventional PLL-based clock multipliers. We propose a phase detector with reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problem of conventional …
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Design of a step-down DC-DC controller integrated circuit with adaptive dead-time control
… control circuitry is implemented as digital delay-locked loop with digital counters as memory elements. In periodic steady state, the switch is controlled to turn on exactly when the body diode starts to conduct current. The conduction loss through MOSFET switch body diode is minimized. In …
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(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
… the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal …
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Models predicting the performance of IC component or PCB channel during electromagnetic interference
… switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference.</p> <p>In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter …
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Techniques for high-performance digital frequency synthesis and phase control
… as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent …
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Low-power high-performance SAR ADC design with digital calibration techniques
… digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.
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Clock multiplication techniques for high-speed I/Os
… reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication …
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Design of energy-efficient high-speed wireline transceiver
… phase calibration method uses a single digital delay-locked loop (DLL) for calibrating all the phases, which makes the calibration process insensitive to the supply voltage level. Thanks to this technique, the proposed multi-Gb/s transceiver operates robustly and energy-efficiently at a very low …
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Overloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimation
… channel is blindly estimated. Multi-user time delay estimation is one of the most important aspects of channel estimation for overloaded array processing. The final chapter of the thesis proposes a low-complexity data-aided time-delay estimation structure for embedding in a Per Survivor …
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Toward realizing power scalable and energy proportional high-speed wireline links
… LC-PLL based clock multi- plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita- tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves power-on-lock in 1ns. The fifth and biggest contribution of this dissertation is the design …
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Circuits for time-domain signal processing
… uses a high resolution digitally controlled delay line (DCDL). Background calibration is used to correct interstage gain errors and sequential switching is used to reduce DCDL non-linearity. Fabricated in 65nm CMOS process, the prototype DTC achieves 1.65ps peak integral non-linearity (INL) …
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.
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Dynamic power management for computing and communication
Power management is essential in state-of-the-art many-core processor and system-on-chip designs due to the ever-increasing demand for performance and the diminishing benefits from technology scaling. With more and more integration of processing cores and functional blocks, aggressive power …
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Energy-efficient wireline transceivers
… circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring …