Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Delay-Locked Loop (DLL)"”.
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Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
Delay-locked loop (DLL)-based clock multipliers have several inherent advantages over conventional PLL-based clock multipliers. We propose a phase detector with reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problem of conventional …
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Models predicting the performance of IC component or PCB channel during electromagnetic interference
… switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference.</p> <p>In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter …
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Techniques for high-performance digital frequency synthesis and phase control
… as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent …
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Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system
… and code tracking of a digital phase-locked loop (PLL) and delay-locked loop (DLL), respectively, is investigated in wideband asynchronous multirate DS-CDMA system. Dynamic Partial Correlation (DPC) method is proposed to evaluate the autocorrelation and its power spectrum density (PSD) …
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Low-power high-performance SAR ADC design with digital calibration techniques
… digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.
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Design of energy-efficient high-speed wireline transceiver
… phase calibration method uses a single digital delay-locked loop (DLL) for calibrating all the phases, which makes the calibration process insensitive to the supply voltage level. Thanks to this technique, the proposed multi-Gb/s transceiver operates robustly and energy-efficiently at a very low …
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Overloaded Array Processing: System Analysis, Signal Extraction Techniques, and Time-delay Estimation
… channel is blindly estimated. Multi-user time delay estimation is one of the most important aspects of channel estimation for overloaded array processing. The final chapter of the thesis proposes a low-complexity data-aided time-delay estimation structure for embedding in a Per Survivor …