Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 17 of 17 for “"Delay Reduction"”.
-
Using tactical flight level resource allocation to alleviate congested en-route airspace
… framework. Two metrics, measuring cumulative delay reduction and fuel burn savings, are used to benchmark the performance of the methodology. A combination of these two metrics is also explored as a means to minimize overall airline operating costs. A subsection of the Northeast Corridor is …
-
Submicron Scaling of Indium Phosphide/indium Gallium Arsenide Heterojunction Bipolar Transistors Toward Terahertz Bandwidths
… to frequencies of fT = 604 GHz though aggressive delay reductions and advanced fabrication processes. Delay reduction is employed by a combination of vertical scaling, lateral scaling, and epitaxial engineering to reduce the transit and charging times of the HBT. The device fabrication process is …
-
Architecture study of a 3D CMOS-NEM FPGA
… together with NEM devices achieves a 33.11% delay reduction, 29.19% power reduction, and 78.23% footprint reduction over the baseline simultaneously, with negligible temperature penalty.
-
Design automation for circuit reliability and energy efficiency
… more common cases. 4) CSL can achieve 6.5% NBTI delay reduction with merely 2.5% area overhead on average. 5) Our modulo functional units, compared to a previous approach, can achieve a 12.5% reduction in area and a 47.1% reduction in delay for a 32-bit mod-3 reducer. For modulo-15 and above, all …
-
DEFINING AND EVALUATING AGILE CONSTRUCTION MANAGEMENT FOR REDUCING TIME DELAYS IN CONSTRUCTION
… completed on schedule. However, schedule delays are common and recurring in construction, inevitably resulting in rework, cost overruns and legal claims. As projects become increasingly complicated, delays arise in a more unpredictable manner. The initial motivation for this research is to …
-
Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
… which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing …
-
A Comprehensive Mixed-Integer Programming Model to Optimize the Performance of Freeway Service Patrol Programs
… due to incidents may cause a substantial delay for drivers and reduce the roadway safety. Effective incident management relies on many tools to lessen the overall impact of crashes, road debris, and disabled vehicles. Many urban areas have adopted freeway service patrol (FSP) programs that …
-
Optimizing Traffic Network Signals Around Railroad Crossings
… transportation goal) and highway traffic delay reduction (a common desire for virtually all of us). Communication and data availability from ITS and the next generation train control are assumed available in SOURCAO. The first step in SOURCAO is to intelligently choose a proper preemption …
-
Evaluation Of The Impacts Of Its Information Strategies On I-4 Corridor
… their routes benefit significantly in terms of delay reduction when incidents occur. It was found that there exists an optimal value for the fraction users with information at which the network performs best. This optimal fraction may be different for different source of information. Also this …
-
Novel Ignition Approaches for Improved Hydrogen Ignition
… 1st injection advanced 2nd injection ignition delay, reducing it from 9.66ms (single-injection) to 0.62ms relative to its start of injection, depending on dwell time. The shortest dwell time (1ms) reduced ignition events due to closely spaced injection interactions, while longer dwell times …
-
New PCM based FPGA architecture and graphene memory cell design
… twin-outputs. The architecture is evaluated over delay and area with different LUT configurations. Experimental results show that on average 50 percent area reduction and 10 percent delay reduction can be achieved with the use of the new PCM based LUTs over SRAM based designs. Also, further …
-
Multilevel logic network synthesis system, SYLON-XTRANS and read-only memory minimization procedure, MINROM
… several transformation procedures for area and delay reduction, which form the multilevel logic network minimization procedure, SYLON-XTRANS-MIN. In Chapter 4, networks synthesized by SYLON-XTRANS are compared with two multilevel logic network synthesisers, MIS 2.1 and SOCRATES. The result shows …
-
Transit Priority Measures at Unsignalized Intersections
Bus delays at unsignalized intersections (UIs) present a unique and persistent operational challenge, particularly for bus routes crossing from the minor approaches of these intersections. In addition, existing transit priority strategies were heavily focused on arterial corridors, leaving the UI …
-
Publishing delay and the usefulness of annual reports in Libya.
… first is to investigate the extent of publishing delay and its determinants in Libya. The second is to find out how useful the annual report is to five user groups in Libya namely the Tax Authority, Academics, Auditors, Banks and the Auditing Authority. Finally, the research also seeks to …
-
Data-driven modeling of air traffic flows for advanced Air Traffic Management
… resulting in high levels of congestion, flight delays and environmental impacts. To sustain the industry growth foreseen and enable more efficient air travel, it is important to develop mechanisms for better understanding and predicting the air traffic flow behavior and performance in order to …
-
Architecture and CAD for nanoscale and 3d FPGA
… are still facing serious challenges in terms of delay, power consumption, and logic density compared to ASICs. FPGA is estimated to be over twenty times less efficient in logic density, over three times worse in delay, and over ten times higher in power consumption compared to a functionally …
-
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
… become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only …