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Showing 1 to 16 of 16 for “"Dataflow graph"”.
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Analysis of CRAY-1S Using Dataflow Graphs.
… the performance of computer systems based on a dataflow graph model is presented. The approach consists of representing the components of a computer system as the nodes of a dataflow graph and the interconnections between the components as the arcs of the dataflow graph. The elapsed time and the …
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Systematic Compilation for Predicated Execution
… the Predicate Analysis System, the Predicate Dataflow Graph, and the Program Decision Logic Optimizer are demonstrated to work synergistically in the compiler to generate efficient code for nonnumeric programs. Using predication, these techniques effectively optimize codes in the presence of …
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Optimizations for acyclic dataflow graphs for hardware-software codesign
… specification is transformed into an internal, dataflow graph (DFG) format. Linear and loop optimizations are then performed to optimize this representation. Linear optimizations are the main topic of discussion in this thesis. The optimized DFG is then synthesized on the reconfigurable platform.
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Parallel and Distributed Just-in-Time Shell Script Compilation
… pipelines. Distributed-PaSh analyzes the dataflow graph of a given script to create highly parallel data pipelines and execute those pipelines in a distributed cluster while giving special attention to data locality and movement. Distributed-PaSh achieves higher performance than single …
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A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System
… Tier2, allows the user to express a problem as a dataflow graph. Actual placing and routing of this graph onto the physical hardware is taken care of through the use of a genetic algorithm. A description of the two languages is presented, followed by example applications. In addition, experimental …
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A Dynamic Application Analysis Framework
… of analyses ahead of time by constructing a graph called a Compact Dataflow Graph (CDG), of the object references used intraprocedurally. The CDG is designed to be independent of the internal representation used by the runtime and general enough to facilitate a large range of dynamic …
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MULTI-SCALE SCHEDULING TECHNIQUES FOR SIGNAL PROCESSING SYSTEMS
… Multicore General Purpose Processors (GPPs), and Graphics Processing Units (GPUs) to heterogeneous combinations of parallel and distributed devices. When a signal processing application is implemented on one of those platforms, the performance critically depends on the scheduling techniques, which …
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A soft coprocessor approach to the development of image and video processing applications on FPGAs
… to enable easy chaining of SCPs, as defined by a Dataflow Graph (DFG). This reduces considerably the amount of data transfer between SCPs and the host processor. <br/><br/><br/>Although hardware optimisation is not a primary concern of this thesis, further contributions facilitate the development …
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End-to-end deep reinforcement learning in computer systems
… execution semantics. I further present RLgraph, my proof-of-concept implementation of this architecture. In RLgraph, algorithm developers can explore novel designs by constructing a high-level data flow graph through combination of logical components. This dataflow graph is independent of …
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Compilers for portable programming of heterogeneous parallel & approximate computing systems
… hardware. This abstraction uses a hierarchical dataflow graph with side effects and vector SIMD instructions. We use this abstraction to define a parallel program representation called HPVM that aims to address both functional portability and performance portability across heterogeneous systems. …
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FPGA-based programmable embedded platform for image processing applications
… environment to the programmer using a dataflow design principle. This gives superior performance when compared to competing alternatives. From this, a three-layered platform has been created which enables the realisation of parallel computing skeletons on FPGA which are used to eciently …
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Heterogeneous parallel virtual machine: A portable program representation and compiler for performance and energy optimizations on heterogeneous parallel systems
… hardware. HPVM is based on a hierarchical dataflow graph with side effects. HPVM successfully supports three important capabilities for programming heterogeneous systems: a compiler intermediate representation (IR), a virtual instruction set (ISA), and a basis for runtime scheduling. We use …
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A methodology for hardware-software codesign
… in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the …
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Komponentenbasierte Softwareentwicklung für datenflußorientierte eingebettete Systeme
Diese Dissertation beschäftigt sich mit den Problemen bei der Entwicklung von effizienter und zuverlässiger Software für eingebettete Systeme. Eingebettete Systeme sind inhärent nebenläufig, was mit einen Grund für ihre hohe Entwurfskomplexität darstellt. Aus dieser Nebenläufigkeit resultiert ein …
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SdrLift: A Domain-Specific Intermediate Hardware Synthesis Framework for Prototyping Software-Defined Radios
… language or a DSL. The SdrLift compiler uses the dataflow graph as an IR to structurally represent the accelerator micro-architecture in which the components correspond to the fine-level and coarse-level Hardware blocks (HW Block) which are either auto-synthesized or integrated from existing …
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Auto-parallelization of machine-learning dataflow graphs for CPU multicores
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01