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Showing 1 to 13 of 13 for “"DPLL"”.
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Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources
… in ADCs when a noisy digital phase locked-loop (DPLL). A time domain DPLL is built by MATLAB Simulink with a phase noise model. The phase noise is obtained from a measured oscillator. When DPLL achieve lock, the time-to-digital converter (TDC) provides an estimate of jitter which is used with an …
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Analysis and design of high order digital phase locked loops
… new design technique for high order Digital PLL (DPLL)systems with a charge pump phase frequency detector component, offering an alternative to the common design practice which is to analyze the DPLL using a linearised model of the analogue PLL. The linear model can only be justified for low order …
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Hybrid solvers for the Boolean Satisfiability problem: an exploration
… Davis-Putnam-Logemann-Loveland solver (DPLL) and the stochastic WalkSAT solver. AmbSAT's design is original and differs from the hybrid solver designs in the research literature. AmbSAT utilizes a DPLL algorithm to lead the search and WalkSAT at appropriate points to aid in the search …
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A new algorithm for the quantified satisfiability problem, based on zero-suppressed binary decision diagrams and memoization
… a variant of BDD, and an adopted version of the DPLL algorithm. It has been implemented in C using the CUDD: Colorado University Decision Diagram package. The capability of ZBDDs in storing sets of subsets efficiently enabled us to store the clauses of a QBF very compactly and let us to embed the …
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Solving optimal satisfiability problems through clause-directed A*
… used to generate optimal candidates, and a DPLL-based SAT solver, used to test feasibility. This paper achieves a substantial performance improvement by introducing a tightly coupled approach, Clause-directed A * (CIA *). ClA* simultaneously directs the search towards assignments that are …
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Interaction of additive and quantization noises in digital PLLs
… in recent decades, discrete-time digital PLLs (DPLLs) are a more recent discipline; most of the literature published dates from the 1990s onwards. Gardner [2] is a pioneer in this area. It is our aim in this work to address the difficulties encountered by Gardner [3] in his investigation of the …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. …
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Algebraic and Logic Solving Methods for Cryptanalysis
… algebraic and logic solving. We focus mainly on DPLL-based SAT solving and techniques that are related to border bases and Gröbner bases. In particular, we describe in detail the Border Basis Algorithm and discuss its specialized version for Boolean polynomials called the Boolean Border Basis …
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A new programmable low noise all digital phase-locked loop architecture
… cost, low noise Programmable All Digital PLL (ADPLL) which utilizes a low cost digital to analog converter (DAC), a voltage controlled crystal oscillator (VCXO), and a field programmable gate array (FPGA). The use of FPGA technology for digital design implementation is universal in the industry …
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SAT Solving Using XOR-OR-AND Normal Forms and Cryptographic Fault Attacks
… techniques, and construct a simple DPLL-based solving framework. Our implementation, 2-Xornado, outperforms modern algebraic and logic solving approaches on many random and some structured cryptographic problems. On the other hand, we apply combined algebraic and logical techniques …
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Exploring Constraint Satisfiability Techniques in Formal Verification
… dissertation, via an integration of local and DPLL-based search approaches. Next, a different hybrid strategy is attempted that takes advantage of the conflicts in the SAT search, which plays a critical role in modern SAT solvers. Usually a learned conflict-induced clause is added back to the …
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Circuits for time-domain signal processing
… improves the non-linearity spur by 12-14dB. The DPLL achieves a figure of merit of -237.2dB which is the best reported among state-of-the-art DPLLs.
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Low-area and power-efficient on-chip clock reference generation
Embargo set by: Seth Robbins for item 115686 Lift date: 2022-08-26T23:57:28Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system