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Showing 1 to 9 of 9 for “"Current mode logic"”.

  1. Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)

    … multipliers. The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power …

    vt Repository record for Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML) (opens in a new tab)

  2. Analysis of MOS Current Mode Logic (MCML) and Implementation of MCML Standard Cell Library for Low-Noise Digital Circuit Design

    <p>MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design …

    calpoly Repository record for Analysis of MOS Current Mode Logic (MCML) and Implementation of MCML Standard Cell Library for Low-Noise Digital Circuit Design (opens in a new tab)

  3. Predictive models for power dissipation in optical transceivers

    … of the network, and a component based power model is developed for it. This model indicates that there are three key power dissipating elements in an optical transceiver: the electrical MUX/DEMUX, the thermoelectric cooler (TE cooler), and the modulator driver amplifier. First, the electrical …

    mit Repository record for Predictive models for power dissipation in optical transceivers (opens in a new tab)

  4. Design of High Performance Threshold Logic Gates

    Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS …

    siu-theses Repository record for Design of High Performance Threshold Logic Gates (opens in a new tab)

  5. Phase Noise in CMOS Phase-Locked Loop Circuits

    … loop as a frequency synthesizer circuit is modeled from the superposition of noises from its building blocks: voltage-controlled oscillator, frequency divider, phase-frequency detector, loop filter and auxiliary input reference clock. A linear time invariant model with additive noise sources …

    lsu-thes Repository record for Phase Noise in CMOS Phase-Locked Loop Circuits (opens in a new tab)

  6. DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES

    … memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of …

    siu-theses Repository record for DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES (opens in a new tab)

  7. Circuit architectures for high speed CMOS clock and data recovery circuits

    As semiconductor process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a …

    uiuc Repository record for Circuit architectures for high speed CMOS clock and data recovery circuits (opens in a new tab)

  8. Design of energy efficient high speed I/O interfaces

    The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.

    uiuc Repository record for Design of energy efficient high speed I/O interfaces (opens in a new tab)