Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 23 for “"Critical paths"”.
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VALIDATION OF CIRCUIT TIMING BEHAVIOR IN THE PRESENCE OF DELAY DEFECTS AND NBTI AGING
… They must be tested appropriately by targeting critical paths in the circuit. Furthermore, reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot carrier injection impact the threshold voltage of a transistor which, in turn, affect path delays. This necessitates …
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Methodologies for Test and Diagnosis of Delay Defects in Integrated Circuits
… Furthermore, a scalable approach to select critical paths from a potentially exponential number of path candidates is presented. Paths and their delay distributions are stored in Zero Suppressed Binary Decision Diagrams. Experimental results on some of the largest ISCAS-89 and ITC-99 …
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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
… of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques …
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Power Distribution Network Analysis and Optimization in Digital VLSI Circuits
… that will cause maximum delay along target critical paths with power/ground bus voltage variation effects. Finally, new techniques for decoupling capacitance placement and power grid area optimization are presented.
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Boosting static timing analysis with programming and algorithmic approaches
… its superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints. We propose a general path search algorithm which can fulfill all practical path constraints and …
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Self-tuning dynamic voltage scaling techniques for processor design
… techniques. First, we introduce a new indirect Critical Path Monitor (CPM) to make a conventional DVS processor adaptive to its given environment. Our CPM is composed of several Slope Generators, each of which generates similar voltage scaling slopes to those of potential critical paths under a …
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Optimal digital system design in deep submicron technology
… which dynamically downsizes transistors on idle paths while maintaining the performance along active critical paths, and apply it to static CMOS circuits.
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Performance-driven chip floorplanning and global routing
… information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This …
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An integrated method for managing complex engineering projects using the design structure matrix and advanced simulation
… various types of information dependencies, a critical dependency path is identified and redundant constraints are removed for the modeling and scheduling analyses. In the modeling module, a generalized process model predicts complex behaviors of iterative processes using advanced simulation …
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DepTracker : tracking JavaScript dependencies on the web
… interactions of JavaScript objects along these critical paths. Current dependency graphs solely include the dependencies that arise from a Web object triggering a new HTTP request. This thesis presents DepTracker, a tool that captures dynamically generated dependencies between JavaScript objects …
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A Resource-constrained CPM (RCPM) Scheduling and Control Technique with Multiple Calendars
This research presents a Resource-constrained Critical Path Method (RCPM) technique that capitalizes on and improves the existing Critical Path Method (CPM) and Resource-Constrained Scheduling (RCS) techniques. A traditional CPM schedule is not realistic since it assumes unlimited resources, some …
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Optimal temporal planning using the plangraph framework
… effects). Futhermore, the planner applies “critical paths” as a backbone for the search in the solution extraction phase, so that irrelevant search branches are pruned early. This improves the performance even in more restricted temporal planning domains. In our experimental evaluation, …
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Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
… proposes a framework that isolates the timing critical paths to a single pipeline stage. At microarchitecture-layer, a dynamic cycle adjustment technique is devised to prevent timing errors in case of excitation of a timing critical path. At application/software-layer, the concept of …
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A systematic approach for architecting a knowledge management system for project management
… and resource dependencies, poor communication of critical information within a project, lack of project control, lack of adequate tools to manage resources, etc. Best practices and industry standards (e.g. Capability Maturity Model, Total Quality Management) have been found to mitigate many of …
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Delay Testing in Nanoscale Technology under Process Variations
… focused on identifying and testing a number of critical paths in the circuit, and aimed at the efficiency of the searching process. However, the statistical circuit model, which better describes the circuit timing behavior under variations, is not yet sufficiently investigated and employed by …
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An analysis tableau and algorithm for flow-shop makespan minimization
… accumulative makespan values), 5. Identifies critical-processing times, 6. Reveals where external improvements would be cost effective, 7. Representation is easily modified for job permutations, 8. Representation is not limited to small flow-shops (low number of jobs and/or machines), 9. …
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Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
… method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values …
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Probabilistic design for emerging memory and nanometer-scale logic
… gate delay, resulting in timing faults on near-critical paths. These low-level faults ultimately propagate to architecture and application levels, often leading to critical system failures. Developing an accurate fault model and injection tool that generates and propagates faults from circuit- …
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Scalable attack modelling in support of security information and event management
… could lead to an attacker gaining access to critical network resources. Key objectives are the investigation of attacks that can be modelled, discovery of attack paths, development of techniques to strengthen networks based on attack paths, and testing scalability for larger networks. The …
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Performance variations due to layout-dependent stress in VLSI circuits
… are selectively used on the gates of the circuit critical paths, at minimal area and power costs. A stress-aware library characterization is performed for FinFET-based standard cells by obtaining stress distributions using finite element simulations on a subset of structures. The stresses are then …
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