Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 34 for “"Coprocessor"”.
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Design and evaluation of an adaptable vector coprocessor for multicores
… efficiency and effectiveness of vector coprocessor sharing policies in multi-core environments. Vector coprocessor sharing is based on an innovative design for a vector lane that forms the building block for the creation of larger vector coprocessors. This innovative lane design contains …
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Vector coprocessor sharing techniques for multicores: performance and energy gains
… for the implementation of a shared vector coprocessor in multicore processors. Sharing an expensive resource among multiple cores increases the efficiency of the functional units and the overall system throughput. The second part of the dissertation regards the evaluation and …
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Design, modeling, and simulation of a Compact Optoelectronic Neural Coprocessor
… objective of the Compact Optoelectronic Neural Coprocessor (CONCOP) project is to build a compact, pixilated, parallel optoelectronic processor capable of running neural network-type algorithms in native hardware.
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Micro-optic elements for a compact opto-electronic integrated neural coprocessor
… the Compact Opto-electronic Integrated Neural coprocessor (COIN coprocessor) project. The COIN coprocessor is an implementation of a feed forward neural network using free-space optical interconnects to communicate between neurons. Prior work on this project had assumed these interconnects …
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Characterization of polygrama green photopolymer for Compact Optoelectronic Integrated Neural (COIN) coprocessor applications
The research described in this thesis is a portion of a larger project within the Photonic Systems Group at MIT to design Compact Optoelectronic Integrated Neural (COIN) co processor [13]. The choice of photopolymers is critical in determining the performance of COIN processors as we look at ways …
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A soft coprocessor approach to the development of image and video processing applications on FPGAs
… starting concept is that of a soft coprocessor (SCP). A set of fundamental soft coprocessors is presented, aimed at implementing some of the key abstractions of Image Algebra. Each soft coprocessor processes an image or video stream, and can be parameterised by its specific …
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Software and Hardware Support for Data Intensive Computing
… chip a commodity microprocessor together with a coprocessor that is designed to run well applications that have poor locality or that require bit manipulations. The coprocessor has a blocked-multithreaded narrow in-order core, and supports vector, streaming, and bit-manipulation computation. It …
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Cryptographic coprocessors for embedded systems
In the field of embedded systems design, coprocessors play an important role as a component to increase performance. Many embedded systems are built around a small General Purpose Processor (GPP). If the GPP cannot meet the performance requirements for a certain operation, a coprocessor can be …
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Accelerating the Performance of a Novel Meshless Method Based on Collocation With Radial Basis Functions By Employing a Graphical Processing Unit as a Parallel Coprocessor
… graphical processing unit (GPU) as a parallel coprocessor. These benefits often include performance improvement over the previous implementations. Furthermore, applications running on graphics processors enjoy superior performance per dollar and performance per watt than implementations built …
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Organic LEDs for optoelectronic neural networks
… Compact Optoelectronic Integrated Neural (COIN) coprocessor. The COIN coprocessor, a prototype artificial neural network implemented in hardware, seeks to implement neural network algorithms in native optoelectronic hardware in order to do parallel type processing in a faster and more efficient …
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Flexible MIPS soft processor architecture
… a more flexible architectural alternative to coprocessor-based solutions. The processor performs out-of-order execution on parallel functional units, it delivers in -order instruction commit and it is compatible with the MIPS-1 Instruction Set Architecture. Amongst many available options, the …
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Evolve : a preliminary multicore architecture for Introspective Computing
… in each core to evolve application-specific coprocessor engines. This thesis work develops two Partner Cores software systems: the Dynamic Partner-Assisted Branch Predictor and the Introspective L2 Memory System (IL2). The branch predictor employs a partner core as a coprocessor engine for …
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A mesh architecture for data management of matrix computations.
… which were previously implemented as coprocessors attached to general purpose processor cores. It is well known that matrix algorithms are highly parallelisable, so the coprocessor generally contains many cores to take advantage of this. However, encapsulating them within the …
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Firmware and gateway for the ACE1 reconfigurable accelerator card
… up and debugging the interface that connects the coprocessor daughtercard to the host server include: problems with the power network, the edge connectors and timing problems with the primary protocol which prevented host-based communications. The options include allowing the daughtercard to …
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Hardware-Software Co-Design for Sensor Nodes in Wireless Networks
… sensor nodes (nodes contain FPGA chips as coprocessors) in wireless networks, it does not estimate power/energy consumption of sensor nodes. So far, no simulators have been developed to evaluate the performance of such flexible nodes in wireless networks. In second section, we present …
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An Optimized Multiple Right-Hand Side Dslash Kernel for Intel Xeon Phi
… to optimize LQCD calculations for floating point coprocessor cards such as GPUs and Intel Xeon Phi Knights Corner (KNC), which boast powerful vector processing units. Most of these efforts in the area of Dslash have focused on single right-hand side solvers. This thesis will present two optimized …
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Benefits of branches in sparsely connected networks
… neuromorphic hardware such as the COIN coprocessor, this thesis explores branched connections networks (BCNs), a kind of neural network in which directed connections may make additional branching connections. It focuses on effective approaches to train sparse BCNs from the bottom up and …
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Exploring Techniques for Providing Privacy in Location-Based Services Nearest Neighbor Query
… transmission time. In this approach, a secure coprocessor is used to provide privacy. We process all information inside the coprocessor to deny adversaries access to any private information. To obfuscate access pattern to external memory location, we use oblivious random access memory …
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Secure and Efficient Implementations of Cryptographic Primitives
… We focus on how to integrate cryptographic coprocessors in an efficient and secure way. The outcome of this research leads to four contributions to hardware security research. First, we propose a programmable and parallel Elliptic Curve Cryptography (ECC) coprocessor architecture. We use a …
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