Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Compiler transformation"”.
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Control Flow Merging: A Compiler Transformation to Mitigate Branch Misprediction by Branch Elimination
… a major performance bottleneck. Existing compiler solutions, such as outcome pre-computation and simple predication, are effective only for loop-invariant conditions or small side-effect-free branches. This work introduces Control Flow Merging (CFM), a compiler transformation that …
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SUDS : automatic parallelization for raw processors
… thesis describes SUDS (Software Un-Do System), a compiler and runtime system that can automatically find and exploit the available concurrency of scalar operations in imperative programs with arbitrary unstructured and unpredictable control flow. The core compiler transformation that enables this …
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Diverse partial memory replication
… memory safety errors. DPMR is an automatic compiler transformation that replicates some subset of an executable's data memory and applies one or more diversity transformations to the replica. DPMR can detect any kind of memory safety error in any part of a program's data memory. Moreover, …
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Eliminating Dynamic Computation Redundancy
… a program in which reuse is likely to occur. The Compiler-directed Computation Reuse (CCR) approach integrates compiler and architecture techniques to exploit execution behavior of these regions. In this approach, the Instruction Set Architecture (ISA) provides a simple interface for the compiler …
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Code Generation for Extreme Scale Parallel Systems
… parallelism. This thesis shows that compiler technology and expressive programming model constructs can help applications more effectively exploit both forms of parallelism. Compilers play an important role in harnessing short vector parallelism supported by cores in modern …
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Low-cost error detection through high-level synthesis
System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters …
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Robust and reliable hardware accelerator design through high-level synthesis
System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters …