Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 23 for “"Coherence protocols"”.
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Synchronization in timestamp-based cache coherence protocols
… support hundreds or thousands of cores. A cache coherence protocol manages the memory cached by these many cores, but the storage overhead required by existing directory-based protocols to track coherence state scales poorly as the number of cores increases. The Tardis cache coherence protocol …
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Design and verification of adaptive cache coherence protocols
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
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Integration and Evaluation of Cache Coherence Protocols for Multiprocessor SoCs
… processors and quantified the efficiency of coherence traffic. Hardware techniques for two main MPSoC architectures were studied: Integration of cache coherence protocols for shared-bus-based MPSoCs and Cache coherence support for non-shared-bus-based MPSoCs. In the shared-bus-based MPSoCs, …
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Optimizing directory-based cache coherence on the RAW architecture
… systems utilizing shared memory, cache coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, the scalability of directory-based schemes makes them ideal for RAW's architecture [1]. Although one such system has been demonstrated …
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Visible synchronization based cache coherence
… with something useful. The issue of cache coherence arises whenever there are multiple copies of a shared datum in different caches of a shared-memory multiprocessor system. It is in order to maintain consistency between these multiple copies that cache coherence protocols are employed. The …
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Proximity coherence for chip-multiprocessors
… to look again at the challenge of cache coherence. The first step in the design process is to analyse the communication behaviour of parallel benchmark suites such as Parsec and SPLASH-2. This thesis presents work detailing the sharing patterns observed when running the full benchmarks on …
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Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors
… specifications, and 3) designing scalable coherence protocols.</p> <p>First, we propose CCA, a new design paradigm for increasing the processor's lifetime performance in the presence of permanent faults in cores. CCA chips rely on a reconfiguration mechanism that allows cores to replace …
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Summarizing multiprocessor program execution with versatile, microarchitecture-independent snapshots
… microarchitectural state resulting from various coherence protocols and cache organizations. The MTR may be quickly updated by each simulated processor during a fast-forwarding phase and optionally stored off-line for reuse. To fill large branch prediction tables, we introduce Branch …
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HyFlow: A High Performance Distributed Software Transactional Memory Framework
… with pluggable support for directory lookup protocols, transactional synchronization and recovery mechanisms, contention management policies, cache coherence protocols, and network communication protocols. HyFlow exports a simple distributed programming model that excludes locks: using (Java …
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Coherencia de Cache en Sistemas de Ficheros para Entornos Distribuidos y Paralelos
… and parallel file systems, but creates data coherence problems due to the potential existence of múltiple copies of the same data. Traditional cache coherence protocols used in distributed and parallel file system are not suitable, however, for parallel applications, where files are usually …
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CRIU-RTX: Remote Thread eXecution using Checkpoint/Restore in Userspace
… challenges of processor interconnects, cache coherence protocols, and memory bandwidth. Significant prior work has addressed this problem by scaling-out application threads across multiple nodes to exploit resources outside the single machine boundary. Prior works have also leveraged …
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Efficient coherence and consistency for specialized memory hierarchies
… a unified global address space, (2) the cache coherence protocol, and (3) the memory consistency model. A unified global address space makes it easier to write programs for heterogeneous systems. Although industry has recently begun to provide a unified global address space across CPUs and …
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Rapid designs for cache coherence protocol engines in Bluespec
… process. We used the RaPED to implement a cache coherence protocol for Shen and Arvind's Commit-Reconcile and Fences (CRF) memory model [1]. The CRF allows scalable implementations of shared memory systems by decomposing memory access operations into simpler instructions. However, the focus for …
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ATAC : A 1000-core cache coherent processor with on-chip optical network
… integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a new …
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Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
… many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip interconnect directly influences the latency and bandwidth of on-chip cache, scalable interconnect is an essential part of on-chip cache design. On the other hand, optimal design of interconnect …
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Hardware implementation and evaluation of the Spandex cache coherence protocol
… bring the need for efficient and flexible cache coherence support. Since different devices like CPUs, GPUs and accelerators have diverse memory demands and different data-sharing patterns, Spandex was proposed to efficiently integrate devices with different cache coherence protocols. The …
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Architectural support to exploit commutativity in shared-memory systems
… and minimal extra complexity, cache coherence protocols, the key component of communication and synchronization in shared-memory systems, can be extended to allow local and concurrent commutative operations. This thesis presents two techniques that leverage this insight to exploit …
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Scalable and Broad Hardware Acceleration through Practical Speculative Parallelism
… already existing techniques, like cache-coherence protocols, for conflict detection, but implementing coherence would add complexity, latency and significant on-chip storage requirement, making these techniques expensive on accelerators. To tackle this challenge, we first propose a new …
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Eliminating on-chip traffic waste: are we there yet?
… study, we use an alternative hardware-software coherence protocol, DeNovo, and apply several optimizations to DeNovo to quantitatively show the traffic inefficiencies of a directory-based MESI protocol. With a fully optimized DeNovo protocol, we can remove most of the traffic inefficiencies …
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Exploiting software information for an efficient memory hierarchy
… in memory hierarchies of today’s systems: (a) coherence, (b) data communication, and (c) data storage. This thesis takes the stand that many of these inefficiencies are a result of today’s software-agnostic hardware design. There is a lot of information in the software that can be exploited to …
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