Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 34 for “"Co-Processor"”.
-
Brute-force resistant Pointer-Authentication using RISC-V co-processor
… In ARMv8.3-A, pointer authentication codes (PACs) are embedded in the upper bits in pointers using tweakable block ciphers like QARMA [1], but these 16-bit PAC space remains susceptible to brute-force attacks, particularly under speculative execution vulnerabilities such as PACMAN [2]. …
-
Acceleration of the discrete element method on a reconfigurable co-processor
… use has been hampered by its extremely computationally demanding nature. The DEM can be run on a parallel computer by farming out different sub-domains onto different processors. However, particles transiting from one sub-domain to another create communication and synchronisation …
-
Systematic Code Partitioning For the Disjoint-Memory Co-Processor Accelerated Execution Model
<p>In the heterogeneous computing execution model, one or more general-purpose processors are accelerated using one or more co-processors. In this model, general-purpose CPUs are generally assigned portions of the software that either do not map well to the available co-processor microarchitectures …
-
A co-processor design to support MPI primitives in configurable multiprocessor designs
… (MIPI) is a widely used standard for inter-processor communication in parallel computers. This standard is normally implemented in software, thus resulting in large communication latencies. A hardware implementation can reduce communication latencies significantly, thereby increasing the …
-
Co-processor offloading applied to passive coherent location with Doppler and bearing data
… algorithm using a ClearSpeed mathematical co-processor. The algorithm is based on non-linear differential correction (also known as the Gauss-Newton method) and uses Doppler and bearing data from a Passive Coherent Location (PCL) radar system. A PCL radar uses a network of receivers to …
-
Design of optoelectronic activation, local memory and weighting circuits for Compact Integrated Optoelectronic Neural (COIN) Co-processor
The Compact Integrated Optoelectronic Neural (COIN) Co-processor, a prototype of artificial neural network implemented in hybrid optics and optoelectronic hardware, aims to implement a multi-layer neural network algorithm by performing parallel and efficient neural computations. In this thesis, we …
-
Reliable Embedded Systems Development
… profits in many fields, it is worthwhile to consider moving key defect reducing strategies from one development area into another. A considerable amount of effort has been contributed to adapt and adopt the success of Agile methods into the embedded domain as defect-reduction methods. …
-
Enabling the use of Heterogeneous Computing for Bioinformatics
The huge amount of information in the encoded sequence of DNA and increasing interest in uncovering new discoveries has spurred interest in accelerating the DNA sequencing and alignment processes. The use of heterogeneous systems, that use different types of computational units, has seen a new …
-
Accelerating software radio astronomy FX correlation with GPU and FPGA co-processors
This thesis attempts to accelerate compute intensive sections of a frequency domain radio astronomy correlator using dedicated co-processors. Two co-processor implementations were made independently with one using reconfigurable hardware (Xilinx Virtex 4LXlOO) and the other uses a graphics …
-
Simulating Nonlinear Neutrino Oscillations on Next-Generation Many-Core Architectures
In this work an astrophysical simulation code, XFLAT, is developed to study neutrino oscillations in supernovae. XFLAT is a hybrid modular code which was designed to utilize multiple levels of parallelism through MPI, OpenMP, and SIMD instructions (vectorization). It can run on both the CPU and the …
-
Implementing Scientific Simulation Codes Tailored for Vector Architectures Using Custom Configurable Computing Machines
… to the availability of massively parallel supercomputers, the implementation of choice for scientific computing problems such as large numerical physical simulations was typically a vector supercomputer. Legacy code still exists optimized for vector supercomputers. Rehosting legacy code often …
-
Firmware and gateway for the ACE1 reconfigurable accelerator card
This thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The aim: to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment to create a seamless environment. Challenges in setting up …
-
A Reconfigurable Implementation of Bayesian Phylogenetic Inference
<p>The field of evolutionary biology has become reliant on the ability to quickly and accurately infer phylogenies, but current software solutions for phylogenetic inference are inadequate to keep up with the growing demands of biologists. FPGA co-processor architectures have been shown to …
-
A lightweight DSP framework for OMAP3530-driven embedded devices
… called MiniDSP, for OMAP3530 heterogeneous dual core SoC to run tasks on its DSP co-processor. This framework is composed of a minimal DSP kernel and a set of programs which run on the ARM A8 master processor. The minimal kernel maintains system stability and initializes the interrupt handler. …
-
Communicatiebewuste plaatsing van data in een gedistribueerd rekensysteem
… doctoraatsproefschrift is de vaststelling dat communicatie cruciaal is in gedistribueerde rekensystemen. Door de evolutie naar een steeds groeiend aantal rekenkernen op één enkele chip, wordt communicatie tussen die kernen steeds belangrijker. Binnen een dergelijk gedistribueerd rekensysteem …
-
Evaluation of GNU Radio Platform Enhanced for Hardware Accelerated Radio Design
… designs. However, they have limitations when it comes to high-speed, high-throughput designs. This limitation can be overcome by introducing a hardware element to the software radio platform. Enhancing GNU Radio for Hardware Accelerated Radio Design project implements such a scheme by augmenting …
-
High-performance matrix multiplication on Intel and FGPA platforms
Matrix multiplication is at the core of high-performance numerical computation. Software methods of accelerating matrix multiplication fall into two categories. One is based on calculation simplification. The other one is based on increasing the memory access efficiency. Also matrix multiplication …
-
Characterization of polygrama green photopolymer for Compact Optoelectronic Integrated Neural (COIN) coprocessor applications
… the Photonic Systems Group at MIT to design Compact Optoelectronic Integrated Neural (COIN) co processor [13]. The choice of photopolymers is critical in determining the performance of COIN processors as we look at ways to increase the diffraction efficiency. The focus of this research was to …
Page 1 of 2