Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"Clockless"”.
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Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic
… of these circuits. Moreover, the majority of clockless design techniques is conceived at circuit level, and is subsequently so fine-grain, that their application to large designs can have unacceptable area costs. Given these considerations, this dissertation presents a new clockless technique, …
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Synthesis Of Self-resetting Stage Logic Pipelines
… As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they …
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Design and implementation of low-latency, low-power reconfigurable on-chip networks
… be part of future many-core chips [17]. Third, clockless repeated links have been shown to be embeddable within a NoC datapath, allowing packets to go from source to destination cores without being latched at intermediate routers. I propose SMARTapp, a design that leverages theses clockless …
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Towards low-power yet high-performance networks-on-chip
… Next demonstrated is a link test chip of two clockless low-swing repeater designs, a self-resetting logic repeater (SRLR) optimized for transmission energy and a voltage-locked repeater (VLR) for transmission delay. This second chip prototype shows that the clockless, single-ended low-swing …
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Circuit design for logic automata
… demonstration of this incrementally extensible, clockless structure, we designed an ALA cell library in 90 nm CMOS technology and established a "pick-and-place" design flow for fast ALA circuit layout. The work flow gracefully aligns the description of computer programs and circuit realizations, …
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Low-swing signaling for energy efficient on-chip networks
… full-swing networks. For the second project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such …
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Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
… accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated.
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Synthetic morphogenesis : space, time, and deformation
… and locally detectable, drawing insights from clockless digital circuits and casting the problem as distributed constraint propagation. In another branch of work, I avoid the problem of timing by making all patterns self- correcting. In self-correcting patterning, I attempt to understand …
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Attacking complexity in logic synthesis of asynchronous circuits
… and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous counterparts. A driving force for a widespread use of asynchronous …