Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 3 of 3 for “"Clock synthesizer"”.
-
Clock synthesizer design with analog and digital phase locked loop
… robust, low-power fast-locking on-chip clocking circuits. The fundamental building block of every clocking circuit used in high-speed links is the Phase-Locked Loop (PLL). This thesis provides an in-depth analysis of basic analog PLL theory, architecture and transistor level design. The …
-
Low jitter phase-locked loop clock synthesis with wide locking range
… employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications …
-
A new programmable low noise all digital phase-locked loop architecture
… flexible and can be configured to operate as a clock and data recovery circuit (CDR), clock multiplier, clock synthesizer, or noise filtering PLL. Using an external VCXO provides a very low noise basis for the PLL and such that we can implement very low bandwidths without sacrificing the quality …