Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 13 of 13 for “"Clock generator"”.
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A spread-spectrum clock generator using phase interpolation for EMI reduction
… layout and simulation of a spread-spectrum clock generator (SSCG) is presented. The SSCG modulates the clock frequency used to switch the digital blocks of the DAC in order to reduce electromagnetic interference (EMI) spurs at the analog output signal of the DAC. Leveraging on a phase …
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Spectrum shaping and its application: spread-spectrum clock generator and circuits for ultra wide band
… of this dissertation deals with Spread-Spectrum Clock Generators (SSCG) aiming at reducing Electro Magnetic Interference (EMI) of clock signals in integrated circuits (IC) design. In particular, the modulation of the clock and the consequent spreading of its spectrum are obtained through a random …
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Systems and circuits for broadband contactless and wireline transceivers
… in the receiver. A novel dual-edge-tracking clock and data recovery loop (DE-CDR) is introduced to retrieve the clock from the received 3-level data stream featuring a fast phase-locking loop (PLL) and a slow delay-locking loop (DLL). The transceiver operates at a DisplayPort rate of 5.2 Gb/s …
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Compact device modeling and millimeter-wave oscillator design for III-V HBT technology
… full circuit simulation. Additionally, tunable clock generator and frequency synthesizer circuits implemented in an indium phosphide (InP) DHBT technology are designed, fabricated, and measured to show the ability of this technology to implement fully integrated sources with moderate power …
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Dynamic amplifiers for analog-to-digital converters
… without extra loading at the input or the clock generator circuitry. The efficacy of this technique is demonstrated by simulating a 4 bit interpolating flash ADC which shows an effective number of bits (ENOB) improvement of 1.5 bits. Third, the non-idealities of the ADC are described and …
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A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter
… ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of …
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Adiabatic Circuits for Power-Constrained Cryptographic Computations
… due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors …
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Design of a phase locked loop based clocking circuit for high speed serial link applications
… over the same old ''lossy'' channels, the clock-frequencies need to scale accordingly and clever I/O links need to be developed. The most crucial component of any high-speed I/O link is the clocking circuitry: clock generator at the transmit (TX) end and clock-recovery unit on the receive …
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Design techniques for temperature insensitive, low phase noise oscillator
A reference clock generator is one of the most important components in many electronic devices. Common clock references are based on quartz crystals which offer high quality factor, good phase noise performance and excellent stability against temperature, voltage and process variation. However, due …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data …
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Digital enhancement techniques for fractional-N frequency synthesizers
… severe energy constraints on the data centers. Clock generators that are essential elements in these systems consume significant power and therefore must be optimized for low power and high performance. The focus of this thesis is on improving the energy efficiency of frequency synthesizers and …
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Clock multiplication techniques for high-speed I/Os
Generation of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by …
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Energy-efficient wireline transceivers
… will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency …