Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 8 of 8 for “"Clock and data recovery (CDR)"”.
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Low-power and energy-efficient wireline receivers
The exponential growth of data processing, ranging from edge devices to cloud computing, requires low-power and energy-efficient wireline data communication. This dissertation proposes innovative ways to accomplish such communication focusing on the receiver side. The first half of the dissertation …
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Modelling and applications of MOS varactors for high-speed CMOS clock and data recovery
The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and …
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Design of a clock and data recovery circuit in 65 nm technology
… fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive …
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Circuit architectures for high speed CMOS clock and data recovery circuits
… process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a major …
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Design of energy-efficient high-speed wireline transceiver
… The power problem permeates both computing and communication systems alike. Especially in the era of Big Data, continuously growing demand for higher communication bandwidth is driving the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power …
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Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.
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Systems and circuits for broadband contactless and wireline transceivers
… have witnessed significant growth in global data traffic, primarily driven by the exponential increase in both the number of users and the amount of data processed by various applications. This has motivated the development of cost- and energy-efficient high-speed interconnects capable of …